Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net (5e47fbe5) · Commits · git / linux-net

.mailmap

+4 −2

Original line number	Diff line number	Diff line
		@@ -340,7 +340,8 @@ Lee Jones <lee@kernel.org> <joneslee@google.com>
		Lee Jones <lee@kernel.org> <lee.jones@canonical.com>
		Lee Jones <lee@kernel.org> <lee.jones@linaro.org>
		Lee Jones <lee@kernel.org> <lee@ubuntu.com>
		Leonard Crestez <leonard.crestez@nxp.com> Leonard Crestez <cdleonard@gmail.com>
		Leonard Crestez <cdleonard@gmail.com> <leonard.crestez@nxp.com>
		Leonard Crestez <cdleonard@gmail.com> <leonard.crestez@intel.com>
		Leonardo Bras <leobras.c@gmail.com> <leonardo@linux.ibm.com>
		Leonard Göhrs <l.goehrs@pengutronix.de>
		Leonid I Ananiev <leonid.i.ananiev@intel.com>
		@@ -497,7 +498,8 @@ Prasad Sodagudi <quic_psodagud@quicinc.com> <psodagud@codeaurora.org>
		Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
		Qais Yousef <qyousef@layalina.io> <qais.yousef@imgtec.com>
		Qais Yousef <qyousef@layalina.io> <qais.yousef@arm.com>
		Quentin Monnet <quentin@isovalent.com> <quentin.monnet@netronome.com>
		Quentin Monnet <qmo@kernel.org> <quentin.monnet@netronome.com>
		Quentin Monnet <qmo@kernel.org> <quentin@isovalent.com>
		Quentin Perret <qperret@qperret.net> <quentin.perret@arm.com>
		Rafael J. Wysocki <rjw@rjwysocki.net> <rjw@sisk.pl>
		Rajeev Nandan <quic_rajeevny@quicinc.com> <rajeevny@codeaurora.org>

Documentation/arch/riscv/vm-layout.rst

+5 −11

Original line number	Diff line number	Diff line
		@@ -144,14 +144,8 @@ passing 0 into the hint address parameter of mmap. On CPUs with an address space
		smaller than sv48, the CPU maximum supported address space will be the default.

		Software can "opt-in" to receiving VAs from another VA space by providing
		a hint address to mmap. A hint address passed to mmap will cause the largest
		address space that fits entirely into the hint to be used, unless there is no
		space left in the address space. If there is no space available in the requested
		address space, an address in the next smallest available address space will be
		returned.

		For example, in order to obtain 48-bit VA space, a hint address greater than
		:code:`1 << 47` must be provided. Note that this is 47 due to sv48 userspace
		ending at :code:`1 << 47` and the addresses beyond this are reserved for the
		kernel. Similarly, to obtain 57-bit VA space addresses, a hint address greater
		than or equal to :code:`1 << 56` must be provided.
		a hint address to mmap. When a hint address is passed to mmap, the returned
		address will never use more bits than the hint address. For example, if a hint
		address of `1 << 40` is passed to mmap, a valid returned address will never use
		bits 41 through 63. If no mappable addresses are available in that range, mmap
		will return `MAP_FAILED`.

Documentation/arch/x86/resctrl.rst

+4 −4

Original line number	Diff line number	Diff line
		@@ -45,7 +45,7 @@ mount options are:
		Enable code/data prioritization in L2 cache allocations.
		"mba_MBps":
		Enable the MBA Software Controller(mba_sc) to specify MBA
		bandwidth in MBps
		bandwidth in MiBps
		"debug":
		Make debug files accessible. Available debug files are annotated with
		"Available only with debug option".
		@@ -526,7 +526,7 @@ threads start using more cores in an rdtgroup, the actual bandwidth may
		increase or vary although user specified bandwidth percentage is same.

		In order to mitigate this and make the interface more user friendly,
		resctrl added support for specifying the bandwidth in MBps as well. The
		resctrl added support for specifying the bandwidth in MiBps as well. The
		kernel underneath would use a software feedback mechanism or a "Software
		Controller(mba_sc)" which reads the actual bandwidth using MBM counters
		and adjust the memory bandwidth percentages to ensure::
		@@ -573,13 +573,13 @@ Memory b/w domain is L3 cache.

		MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...

		Memory bandwidth Allocation specified in MBps
		Memory bandwidth Allocation specified in MiBps
		---------------------------------------------

		Memory bandwidth domain is L3 cache.
		::

		MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...
		MB:<cache_id0>=bw_MiBps0;<cache_id1>=bw_MiBps1;...

		Slow Memory Bandwidth Allocation (SMBA)
		---------------------------------------

Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml

+1 −1

Original line number	Diff line number	Diff line
		@@ -270,7 +270,7 @@ examples:

		port {
		ov7251_ep: endpoint {
		data-lanes = <0 1>;
		data-lanes = <0>;
		link-frequencies = /bits/ 64 <240000000 319200000>;
		remote-endpoint = <&csiphy3_ep>;
		};

Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml

+43 −6

Original line number	Diff line number	Diff line
		@@ -14,9 +14,6 @@ description: The Nomadik I2C host controller began its life in the ST
		maintainers:
		- Linus Walleij <linus.walleij@linaro.org>

		allOf:
		- $ref: /schemas/i2c/i2c-controller.yaml#

		# Need a custom select here or 'arm,primecell' will match on lots of nodes
		select:
		properties:
		@@ -24,21 +21,23 @@ select:
		contains:
		enum:
		- st,nomadik-i2c
		- mobileye,eyeq5-i2c
		required:
		- compatible

		properties:
		compatible:
		oneOf:
		# The variant found in STn8815
		- items:
		- const: st,nomadik-i2c
		- const: arm,primecell
		# The variant found in DB8500
		- items:
		- const: stericsson,db8500-i2c
		- const: st,nomadik-i2c
		- const: arm,primecell
		- items:
		- const: mobileye,eyeq5-i2c
		- const: arm,primecell

		reg:
		maxItems: 1
		@@ -55,7 +54,7 @@ properties:
		- items:
		- const: mclk
		- const: apb_pclk
		# Clock name in DB8500
		# Clock name in DB8500 or EyeQ5
		- items:
		- const: i2cclk
		- const: apb_pclk
		@@ -70,6 +69,16 @@ properties:
		minimum: 1
		maximum: 400000

		mobileye,olb:
		$ref: /schemas/types.yaml#/definitions/phandle-array
		items:
		- items:
		- description: Phandle to OLB system controller node.
		- description: Platform-wide controller ID (integer starting from zero).
		description:
		The phandle pointing to OLB system controller node, with the I2C
		controller index.

		required:
		- compatible
		- reg
		@@ -79,6 +88,20 @@ required:

		unevaluatedProperties: false

		allOf:
		- $ref: /schemas/i2c/i2c-controller.yaml#
		- if:
		properties:
		compatible:
		contains:
		const: mobileye,eyeq5-i2c
		then:
		required:
		- mobileye,olb
		else:
		properties:
		mobileye,olb: false

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/irq.h>
		@@ -111,5 +134,19 @@ examples:
		clocks = <&i2c0clk>, <&pclki2c0>;
		clock-names = "mclk", "apb_pclk";
		};
		- \|
		#include <dt-bindings/interrupt-controller/mips-gic.h>
		i2c@300000 {
		compatible = "mobileye,eyeq5-i2c", "arm,primecell";
		reg = <0x300000 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <400000>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&i2c_ser_clk>, <&i2c_clk>;
		clock-names = "i2cclk", "apb_pclk";
		mobileye,olb = <&olb 0>;
		};

		...