Commit 5e4c16fe authored by Khaled Almahallawy's avatar Khaled Almahallawy Committed by Rodrigo Vivi
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drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned 



Currently, with MFD/pin assignment D, the driver clears the pipe reset bit
of lane 1 which is not owned by display. This causes the display
to block S0iX.

By not clearing this bit for lane 1 and keeping whatever default, S0ix
started to work. This is already what the driver does at the end
of the phy lane reset sequence (Step#8)

Bspec: 65451
Fixes: 619a06db ("drm/i915/mtl: Reset only one lane in case of MFD")
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarKhaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231005001310.154396-1-khaled.almahallawy@intel.com


(cherry picked from commit 4a07f063)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 58720809

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+1 −2
Original line number Diff line number Diff line
@@ -2553,8 +2553,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, 
		drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",

			 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);



	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),

		     XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),

	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset,

		     lane_pipe_reset);



	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),