Commit 5e66f6ea authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Add some missing HDMI registers for DCN3x 



This commit add some missing HDMI control registers to DCN3x.

Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e0238740

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h

+3 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 


#define DCCG_REG_LIST_DCN30() \

	DCCG_REG_LIST_DCN2(),\

	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
@@ -41,6 +42,8 @@ 


#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \

	DCCG_MASK_SH_LIST_DCN2(mask_sh),\

	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\

	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\

	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

+6 −0
Original line number Diff line number Diff line
@@ -34,12 +34,14 @@ 
	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\

	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\

	SR(PHYASYMCLK_CLOCK_CNTL),\

	SR(PHYBSYMCLK_CLOCK_CNTL),\

	SR(PHYCSYMCLK_CLOCK_CNTL),\

	SR(PHYDSYMCLK_CLOCK_CNTL),\

	SR(PHYESYMCLK_CLOCK_CNTL),\

	SR(DPSTREAMCLK_CNTL),\

	SR(HDMISTREAMCLK_CNTL),\

	SR(SYMCLK32_SE_CNTL),\

	SR(SYMCLK32_LE_CNTL),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
@@ -78,6 +80,8 @@ 
	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\

	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\

	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\

	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\

	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\

	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\

	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\

	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
@@ -92,6 +96,8 @@ 
	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\

	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\

	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\

	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

+4 −0
Original line number Diff line number Diff line
@@ -311,6 +311,10 @@ 
#define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

#define mmPHYFSYMCLK_CLOCK_CNTL                                                                        0x0057

#define mmPHYFSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a

#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2

#define mmHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a

#define mmHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2

















// addressBlock: dce_dc_dccg_dccg_dfs_dispdec

























drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h



+5
−0






























Original line number
Diff line number
Diff line







@@ -1189,6 +1189,11 @@







#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4









#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_FORCE_EN_MASK                                                       0x00000001L









#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L









//HDMICHARCLK0_CLOCK_CNTL









#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0









#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4









#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L









#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L

























// addressBlock: dce_dc_dccg_dccg_dfs_dispdec

























drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h



+4
−0






























Original line number
Diff line number
Diff line







@@ -213,6 +213,8 @@







#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2









#define regDTBCLK_DTO3_MODULO                                                                           0x0022









#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2









#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a









#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2









#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052









#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2









#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053








@@ -233,6 +235,8 @@







#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2









#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063









#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2









#define regHDMISTREAMCLK_CNTL                                                                           0x0059









#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2

























// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec