Commit 5ea7fe65 authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
Browse files

drm/xe: Move some per-engine register definitions to the engine header 



Although we only work with the RCS instances today, the
FF_SLICE_CS_CHICKEN1[1,2] CS_DEBUG_MODE1, CS_CHICKEN1, and
FF_THREAD_MODE registers all have instances on both the RCS and CCS
engines.  Convert these to parameterized macros and move them to the
engine register header.

Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-12-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent bc17ec0b

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+21 −0
Original line number Diff line number Diff line
@@ -39,6 +39,9 @@ 
#define RING_MI_MODE(base)			XE_REG((base) + 0x9c)

#define RING_NOPID(base)			XE_REG((base) + 0x94)



#define FF_THREAD_MODE(base)			XE_REG((base) + 0xa0)

#define   FF_TESSELATION_DOP_GATE_DISABLE	BIT(19)



#define RING_IMR(base)				XE_REG((base) + 0xa8)



#define RING_EIR(base)				XE_REG((base) + 0xb0)
@@ -60,6 +63,16 @@ 
#define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)

#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)



#define FF_SLICE_CS_CHICKEN1(base)		XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)

#define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)



#define FF_SLICE_CS_CHICKEN2(base)		XE_REG((base) + 0xe4, XE_REG_OPTION_MASKED)

#define   PERF_FIX_BALANCING_CFE_DISABLE	REG_BIT(15)



#define CS_DEBUG_MODE1(base)			XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)

#define   FF_DOP_CLOCK_GATE_DISABLE		REG_BIT(1)

#define   REPLAY_MODE_GRANULARITY		REG_BIT(0)



#define RING_BBADDR(base)			XE_REG((base) + 0x140)

#define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
@@ -115,6 +128,14 @@ 
#define RING_EXECLIST_CONTROL(base)		XE_REG((base) + 0x550)

#define	  EL_CTRL_LOAD				REG_BIT(0)



#define CS_CHICKEN1(base)			XE_REG((base) + 0x580, XE_REG_OPTION_MASKED)

#define   PREEMPT_GPGPU_LEVEL(hi, lo)		(((hi) << 2) | ((lo) << 1))

#define   PREEMPT_GPGPU_MID_THREAD_LEVEL	PREEMPT_GPGPU_LEVEL(0, 0)

#define   PREEMPT_GPGPU_THREAD_GROUP_LEVEL	PREEMPT_GPGPU_LEVEL(0, 1)

#define   PREEMPT_GPGPU_COMMAND_LEVEL		PREEMPT_GPGPU_LEVEL(1, 0)

#define   PREEMPT_GPGPU_LEVEL_MASK		PREEMPT_GPGPU_LEVEL(1, 1)

#define   PREEMPT_3D_OBJECT_LEVEL		REG_BIT(0)



#define VDBOX_CGCTL3F08(base)                  XE_REG((base) + 0x3f08)

#define   CG3DDISHRS_CLKGATE_DIS               REG_BIT(5)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+0 −18
Original line number Diff line number Diff line
@@ -60,26 +60,8 @@ 
#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)

#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)



#define FF_SLICE_CS_CHICKEN1			XE_REG(0x20e0, XE_REG_OPTION_MASKED)

#define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)



#define FF_SLICE_CS_CHICKEN2			XE_REG(0x20e4, XE_REG_OPTION_MASKED)

#define   PERF_FIX_BALANCING_CFE_DISABLE	REG_BIT(15)



#define CS_DEBUG_MODE1				XE_REG(0x20ec, XE_REG_OPTION_MASKED)

#define   FF_DOP_CLOCK_GATE_DISABLE		REG_BIT(1)

#define   REPLAY_MODE_GRANULARITY		REG_BIT(0)



#define PS_INVOCATION_COUNT			XE_REG(0x2348)



#define CS_CHICKEN1				XE_REG(0x2580, XE_REG_OPTION_MASKED)

#define   PREEMPT_GPGPU_LEVEL(hi, lo)		(((hi) << 2) | ((lo) << 1))

#define   PREEMPT_GPGPU_MID_THREAD_LEVEL	PREEMPT_GPGPU_LEVEL(0, 0)

#define   PREEMPT_GPGPU_THREAD_GROUP_LEVEL	PREEMPT_GPGPU_LEVEL(0, 1)

#define   PREEMPT_GPGPU_COMMAND_LEVEL		PREEMPT_GPGPU_LEVEL(1, 0)

#define   PREEMPT_GPGPU_LEVEL_MASK		PREEMPT_GPGPU_LEVEL(1, 1)

#define   PREEMPT_3D_OBJECT_LEVEL		REG_BIT(0)



#define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)

#define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)

#define CCS_AUX_INV				XE_REG(0x4208)

drivers/gpu/drm/xe/regs/xe_regs.h

+0 −3
Original line number Diff line number Diff line
@@ -45,9 +45,6 @@ 
#define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)

#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)



#define FF_THREAD_MODE				XE_REG(0x20a0)

#define   FF_TESSELATION_DOP_GATE_DISABLE	BIT(19)



#define TIMESTAMP_OVERRIDE					XE_REG(0x44074)

#define   TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	REG_GENMASK(15, 12)

#define   TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK		REG_GENMASK(9, 0)

drivers/gpu/drm/xe/xe_wa.c

+9 −7
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
static const struct xe_rtp_entry_sr engine_was[] = {

	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),

	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE,

	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),

			     FF_TESSELATION_DOP_GATE_DISABLE))

	},

	{ XE_RTP_NAME("1409804808"),
@@ -320,7 +320,8 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	},

	{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE))

	  XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),

			     FF_DOP_CLOCK_GATE_DISABLE))

	},

	{ XE_RTP_NAME("1406941453"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
@@ -328,7 +329,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	},

	{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1,

	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),

			     FFSC_PERCTX_PREEMPT_CTRL))

	},
@@ -419,7 +420,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	{ XE_RTP_NAME("16015675438"),

	  XE_RTP_RULES(PLATFORM(DG2),

		       FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2,

	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),

			     PERF_FIX_BALANCING_CFE_DISABLE))

	},

	{ XE_RTP_NAME("18028616096"),
@@ -481,7 +482,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),

		       ENGINE_CLASS(RENDER),

		       FUNC(xe_rtp_match_first_gslice_fused_off)),

	  XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1,

	  XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1(RENDER_RING_BASE),

			     REPLAY_MODE_GRANULARITY))

	},

	{ XE_RTP_NAME("22010960976, 14013347512"),
@@ -540,7 +541,8 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	},

	{ XE_RTP_NAME("16015675438"),

	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2, PERF_FIX_BALANCING_CFE_DISABLE))

	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),

			     PERF_FIX_BALANCING_CFE_DISABLE))

	},

	{ XE_RTP_NAME("14014999345"),

	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
@@ -622,7 +624,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	},

	{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),

	  XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1,

	  XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),

				   PREEMPT_GPGPU_LEVEL_MASK,

				   PREEMPT_GPGPU_THREAD_GROUP_LEVEL))

	},