Commit 5eb2e785 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/display: use x100 version for full version and release 



Use x100, or ver * 100 + rel, versions for full IP version checks,
similar to what xe driver does:

- Replace IP_VER(14, 1) inline with 1401, etc.

- Convert DISPLAY_VER_FULL() to DISPLAY_VERx100()

- Convert IS_DISPLAY_VER_FULL() to IS_DISPLAY_VERx100()

- Convert IS_DISPLAY_VER_STEP() to IS_DISPLAY_VERx100_STEP()

This makes ver.rel versions easier to use, follows the xe driver
pattern, and drops the dependency on the IP_VER() macro.

v2: Rebase, drop IP_VER() from xe compat headers

v3: Rebase

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029155536.753413-1-jani.nikula@intel.com
parent 3291b741

drivers/gpu/drm/i915/display/intel_atomic_plane.c

+2 −2
Original line number Diff line number Diff line
@@ -1026,8 +1026,8 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) 
		vsub = 1;



		/* Wa_16023981245 */

		if ((DISPLAY_VER_FULL(i915) == IP_VER(20, 0) ||

		     DISPLAY_VER_FULL(i915) == IP_VER(30, 0)) &&

		if ((DISPLAY_VERx100(i915) == 2000 ||

		     DISPLAY_VERx100(i915) == 3000) &&

		     src_x % 2 != 0)

			hsub = 2;

	} else {

drivers/gpu/drm/i915/display/intel_bw.c

+1 −1
Original line number Diff line number Diff line
@@ -743,7 +743,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) 
	if (!HAS_DISPLAY(dev_priv))

		return;



	if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv))

	if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))

		xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);

	else if (DISPLAY_VER(dev_priv) >= 14)

		tgl_get_bw_info(dev_priv, &mtl_sa_info);

drivers/gpu/drm/i915/display/intel_cdclk.c

+3 −3
Original line number Diff line number Diff line
@@ -2058,8 +2058,8 @@ static bool pll_enable_wa_needed(struct intel_display *display) 
{

	struct drm_i915_private *dev_priv = to_i915(display->drm);



	return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) ||

		DISPLAY_VER_FULL(display) == IP_VER(14, 0) ||

	return (DISPLAY_VERx100(display) == 2000 ||

		DISPLAY_VERx100(display) == 1400 ||

		IS_DG2(dev_priv)) &&

		display->cdclk.hw.vco > 0;

}
@@ -3852,7 +3852,7 @@ void intel_init_cdclk_hooks(struct intel_display *display) 
	} else if (DISPLAY_VER(display) >= 20) {

		display->funcs.cdclk = &rplu_cdclk_funcs;

		display->cdclk.table = xe2lpd_cdclk_table;

	} else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) {

	} else if (DISPLAY_VERx100(display) >= 1401) {

		display->funcs.cdclk = &rplu_cdclk_funcs;

		display->cdclk.table = xe2hpd_cdclk_table;

	} else if (DISPLAY_VER(display) >= 14) {

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+2 −2
Original line number Diff line number Diff line
@@ -2286,13 +2286,13 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, 
		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {

			if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)

				return xe3lpd_c20_dp_edp_tables;

			if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))

			if (DISPLAY_VERx100(display) == 1401)

				return xe2hpd_c20_edp_tables;

		}



		if (DISPLAY_VER(display) >= 30)

			return xe3lpd_c20_dp_edp_tables;

		else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))

		else if (DISPLAY_VERx100(display) == 1401)

			return xe2hpd_c20_dp_tables;

		else

			return mtl_c20_dp_tables;

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -273,7 +273,7 @@ 
#define _XE2HPD_C20_A_MPLLB_CFG		0xCCC2

#define _XE2HPD_C20_B_MPLLB_CFG		0xCCB6



#define _IS_XE2HPD_C20(i915)	(DISPLAY_VER_FULL(i915) == IP_VER(14, 1))

#define _IS_XE2HPD_C20(i915)	(DISPLAY_VERx100(i915) == 1401)



#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \

		((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx))