Commit 5eb64f2b authored by Varshini Rajendran's avatar Varshini Rajendran Committed by Claudiu Beznea
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ARM: at91: add support in SoC driver for new sam9x7 



Add support for SAM9X7 SoC in the SoC driver.

Signed-off-by: default avatarVarshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20240729070711.1990605-1-varshini.rajendran@microchip.com


Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent 2488bde9

drivers/soc/atmel/soc.c

+23 −0
Original line number Diff line number Diff line
@@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = { 
		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,

		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),

#endif

#ifdef CONFIG_SOC_SAM9X7

	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,

		 "sam9x70", "sam9x7"),

	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,

		 "sam9x72", "sam9x7"),

	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,

		 "sam9x75", "sam9x7"),

	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,

		 "sam9x75 16MB DDR2 SiP", "sam9x7"),

	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,

		 "sam9x75 64MB DDR2 SiP", "sam9x7"),

	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,

		 "sam9x75 125MB DDR3L SiP ", "sam9x7"),

	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,

		 "sam9x75 250MB DDR3L SiP", "sam9x7"),

#endif

#ifdef CONFIG_SOC_SAMA5

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,

drivers/soc/atmel/soc.h

+9 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs); 
#define AT91SAM9X5_CIDR_MATCH		0x019a05a0

#define AT91SAM9N12_CIDR_MATCH		0x019a07a0

#define SAM9X60_CIDR_MATCH		0x019b35a0

#define SAM9X7_CIDR_MATCH		0x09750020

#define SAMA7G5_CIDR_MATCH		0x00162100



#define AT91SAM9M11_EXID_MATCH		0x00000001
@@ -66,6 +67,14 @@ at91_soc_init(const struct at91_soc *socs); 
#define SAM9X60_D1G_EXID_MATCH		0x00000010

#define SAM9X60_D6K_EXID_MATCH		0x00000011



#define SAM9X70_EXID_MATCH		0x00000005

#define SAM9X72_EXID_MATCH		0x00000004

#define SAM9X75_D1G_EXID_MATCH		0x00000018

#define SAM9X75_D2G_EXID_MATCH		0x00000020

#define SAM9X75_D1M_EXID_MATCH		0x00000003

#define SAM9X75_D5M_EXID_MATCH		0x00000010

#define SAM9X75_EXID_MATCH		0x00000000



#define SAMA7G51_EXID_MATCH		0x3

#define SAMA7G52_EXID_MATCH		0x2

#define SAMA7G53_EXID_MATCH		0x1