Commit 5ec06904 authored by Roger Quadros's avatar Roger Quadros Committed by Vignesh Raghavendra
Browse files

arm64: dts: ti: k3-am64-main: Add GPMC memory controller node 



The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
  - Asynchronous SRAM-like memories and ASICs
  - Asynchronous, synchronous, and page mode burst NOR flash
  - NAND flash
  - Pseudo-SRAM devices

Signed-off-by: default avatarRoger Quadros <rogerq@kernel.org>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarBryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20220802104456.11069-2-rogerq@kernel.org
parent f42f6f9e

arch/arm64/boot/dts/ti/k3-am64-main.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -1328,4 +1328,23 @@ rng: rng@40910000 { 
			status = "disabled"; /* Used by OP-TEE */

		};

	};



	gpmc0: memory-controller@3b000000 {

		compatible = "ti,am64-gpmc";

		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 80 0>;

		clock-names = "fck";

		reg = <0x00 0x03b000000 0x00 0x400>,

		      <0x00 0x050000000 0x00 0x8000000>;

		reg-names = "cfg", "data";

		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

		gpmc,num-cs = <3>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

		#size-cells = <1>;

		interrupt-controller;

		#interrupt-cells = <2>;

		gpio-controller;

		#gpio-cells = <2>;

	};

};

arch/arm64/boot/dts/ti/k3-am642-evm.dts

+4 −0
Original line number Diff line number Diff line
@@ -676,3 +676,7 @@ &main_mcan1 { 
	pinctrl-0 = <&main_mcan1_pins_default>;

	phys = <&transceiver2>;

};



&gpmc0 {

	status = "disabled";

};

arch/arm64/boot/dts/ti/k3-am642-sk.dts

+4 −0
Original line number Diff line number Diff line
@@ -607,3 +607,7 @@ &main_mcan0 { 
&main_mcan1 {

	status = "disabled";

};



&gpmc0 {

	status = "disabled";

};