Commit 5ef0832c authored by Wangao Wang's avatar Wangao Wang Committed by Hans Verkuil
Browse files

media: qcom: iris: Add intra refresh support for encoder



Add support for V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD and
V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE controls.

Reviewed-by: default avatarDikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Signed-off-by: default avatarWangao Wang <wangao.wang@oss.qualcomm.com>
Signed-off-by: default avatarBryan O'Donoghue <bod@kernel.org>
Signed-off-by: default avatarHans Verkuil <hverkuil+cisco@kernel.org>
parent 874eca6d
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+34 −0
Original line number Diff line number Diff line
@@ -108,6 +108,10 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id)
		return HFLIP;
	case V4L2_CID_VFLIP:
		return VFLIP;
	case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE:
		return IR_TYPE;
	case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD:
		return IR_PERIOD;
	default:
		return INST_FW_CAP_MAX;
	}
@@ -205,6 +209,10 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id)
		return V4L2_CID_HFLIP;
	case VFLIP:
		return V4L2_CID_VFLIP;
	case IR_TYPE:
		return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE;
	case IR_PERIOD:
		return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD;
	default:
		return 0;
	}
@@ -962,6 +970,32 @@ int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
					     &hfi_val, sizeof(u32));
}

int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
{
	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
	struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
	u32 ir_period = inst->fw_caps[cap_id].value;
	u32 ir_type = 0;

	if (inst->fw_caps[IR_TYPE].value ==
			V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) {
		if (vb2_is_streaming(q))
			return 0;
		ir_type = HFI_PROP_IR_RANDOM_PERIOD;
	} else if (inst->fw_caps[IR_TYPE].value ==
			V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) {
		ir_type = HFI_PROP_IR_CYCLIC_PERIOD;
	} else {
		return -EINVAL;
	}

	return hfi_ops->session_set_property(inst, ir_type,
					     HFI_HOST_FLAGS_NONE,
					     iris_get_port_info(inst, cap_id),
					     HFI_PAYLOAD_U32,
					     &ir_period, sizeof(u32));
}

int iris_set_properties(struct iris_inst *inst, u32 plane)
{
	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_properties(struct iris_inst *inst, u32 plane);

#endif
+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ enum hfi_rate_control {
#define HFI_PROP_QP_PACKED			0x0300012e
#define HFI_PROP_MIN_QP_PACKED			0x0300012f
#define HFI_PROP_MAX_QP_PACKED			0x03000130
#define HFI_PROP_IR_RANDOM_PERIOD		0x03000131
#define HFI_PROP_TOTAL_BITRATE			0x0300013b
#define HFI_PROP_MAX_GOP_FRAMES			0x03000146
#define HFI_PROP_MAX_B_FRAMES			0x03000147
@@ -113,6 +114,7 @@ enum hfi_flip {
#define HFI_PROP_AV1_FILM_GRAIN_PRESENT	0x03000180
#define HFI_PROP_AV1_SUPER_BLOCK_ENABLED	0x03000181
#define HFI_PROP_AV1_OP_POINT			0x03000182
#define HFI_PROP_IR_CYCLIC_PERIOD		0x0300017E
#define HFI_PROP_OPB_ENABLE			0x03000184
#define HFI_PROP_AV1_TILE_ROWS_COLUMNS		0x03000187
#define HFI_PROP_AV1_DRAP_CONFIG		0x03000189
+2 −0
Original line number Diff line number Diff line
@@ -153,6 +153,8 @@ enum platform_inst_fw_cap_type {
	ROTATION,
	HFLIP,
	VFLIP,
	IR_TYPE,
	IR_PERIOD,
	INST_FW_CAP_MAX,
};

+19 −0
Original line number Diff line number Diff line
@@ -721,6 +721,25 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
			CAP_FLAG_DYNAMIC_ALLOWED,
		.set = iris_set_flip,
	},
	{
		.cap_id = IR_TYPE,
		.min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
		.max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC,
		.step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) |
			BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC),
		.value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
	},
	{
		.cap_id = IR_PERIOD,
		.min = 0,
		.max = INT_MAX,
		.step_or_mask = 1,
		.value = 0,
		.flags = CAP_FLAG_OUTPUT_PORT |
			CAP_FLAG_DYNAMIC_ALLOWED,
		.set = iris_set_ir_period,
	},
};

static struct platform_inst_caps platform_inst_cap_sm8550 = {