Commit 5f459cb0 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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dt-bindings: soc: tegra-pmc: Document core power domain 



All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Document the new core power domain properties.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c4a41429

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml

+35 −0
Original line number Diff line number Diff line
@@ -301,6 +301,33 @@ patternProperties: 


    additionalProperties: false



  core-domain:

    type: object

    description: |

      The vast majority of hardware blocks of Tegra SoC belong to a

      Core power domain, which has a dedicated voltage rail that powers

      the blocks.



    properties:

      operating-points-v2:

        description:

          Should contain level, voltages and opp-supported-hw property.

          The supported-hw is a bitfield indicating SoC speedo or process

          ID mask.



      "#power-domain-cells":

        const: 0



    required:

      - operating-points-v2

      - "#power-domain-cells"



    additionalProperties: false



  core-supply:

    description:

      Phandle to voltage regulator connected to the SoC Core power rail.



required:

  - compatible

  - reg
@@ -325,6 +352,7 @@ examples: 
    tegra_pmc: pmc@7000e400 {

              compatible = "nvidia,tegra210-pmc";

              reg = <0x7000e400 0x400>;

              core-supply = <&regulator>;

              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;

              clock-names = "pclk", "clk32k_in";

              #clock-cells = <1>;
@@ -338,17 +366,24 @@ examples: 
              nvidia,core-power-req-active-high;

              nvidia,sys-clock-req-active-high;



              pd_core: core-domain {

                      operating-points-v2 = <&core_opp_table>;

                      #power-domain-cells = <0>;

              };



              powergates {

                    pd_audio: aud {

                            clocks = <&tegra_car TEGRA210_CLK_APE>,

                                     <&tegra_car TEGRA210_CLK_APB2APE>;

                            resets = <&tegra_car 198>;

                            power-domains = <&pd_core>;

                            #power-domain-cells = <0>;

                    };



                    pd_xusbss: xusba {

                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;

                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;

                            power-domains = <&pd_core>;

                            #power-domain-cells = <0>;

                    };

              };