Commit 5f571c61 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add gfx v9_4_4 ip block 



Add gfx v9_4_4 ip block support

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLe Ma <le.ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a6bcffa5

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+5 −2
Original line number Diff line number Diff line
@@ -1308,6 +1308,7 @@ static int amdgpu_device_asic_init(struct amdgpu_device *adev) 
	amdgpu_asic_pre_asic_init(adev);



	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||

	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||

	    amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {

		amdgpu_psp_wait_for_bootloader(adev);

		ret = amdgpu_atomfirmware_asic_init(adev, true);
@@ -5126,6 +5127,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, 
	/* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */

	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||

	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||

	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||

	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))

		amdgpu_ras_resume(adev);

	return 0;
@@ -6275,7 +6277,8 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) 
		amdgpu_put_xgmi_hive(hive);

	}

	ras = amdgpu_ras_get_context(adev);

	if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) &&

	if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||

	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) &&

	    ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery))

		return PCI_ERS_RESULT_RECOVERED;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+9 −2
Original line number Diff line number Diff line
@@ -1424,7 +1424,8 @@ static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 
	 * harvest configuration.

	 */

	if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&

	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) {

	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) &&

	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) {

		if ((adev->pdev->device == 0x731E &&

			(adev->pdev->revision == 0xC6 ||

			 adev->pdev->revision == 0xC7)) ||
@@ -1677,6 +1678,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(9, 4, 1):

	case IP_VERSION(9, 4, 2):

	case IP_VERSION(9, 4, 3):

	case IP_VERSION(9, 4, 4):

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		break;

	case IP_VERSION(10, 1, 10):
@@ -1729,6 +1731,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(9, 4, 1):

	case IP_VERSION(9, 4, 2):

	case IP_VERSION(9, 4, 3):

	case IP_VERSION(9, 4, 4):

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);

		break;

	case IP_VERSION(10, 1, 10):
@@ -2019,6 +2022,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		break;

	case IP_VERSION(9, 4, 3):

	case IP_VERSION(9, 4, 4):

		amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);

		break;

	case IP_VERSION(10, 1, 10):
@@ -2243,6 +2247,7 @@ static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 
{

	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(9, 4, 3):

	case IP_VERSION(9, 4, 4):

		aqua_vanjaram_init_soc_config(adev);

		break;

	default:
@@ -2468,6 +2473,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(9, 4, 1):

	case IP_VERSION(9, 4, 2):

	case IP_VERSION(9, 4, 3):

	case IP_VERSION(9, 4, 4):

		adev->family = AMDGPU_FAMILY_AI;

		break;

	case IP_VERSION(9, 1, 0):
@@ -2539,7 +2545,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0))

		adev->gmc.xgmi.supported = true;



	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))

	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||

	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4))

		adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0);



	/* set NBIO version */

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+2 −1
Original line number Diff line number Diff line
@@ -539,7 +539,8 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) 
	}



	ras = amdgpu_ras_get_context(adev);

	if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) &&

	if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||

	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) &&

		ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery)) {

		spin_unlock(&kiq->ring_lock);

		return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −0
Original line number Diff line number Diff line
@@ -881,6 +881,7 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 
				gc_ver == IP_VERSION(9, 4, 1) ||

				gc_ver == IP_VERSION(9, 4, 2) ||

				gc_ver == IP_VERSION(9, 4, 3) ||

				gc_ver == IP_VERSION(9, 4, 4) ||

				gc_ver >= IP_VERSION(10, 3, 0));



	if (!amdgpu_sriov_xnack_support(adev))

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+2 −1
Original line number Diff line number Diff line
@@ -1742,7 +1742,8 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 
			amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);



	if (!adev->bios &&

	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))

	    (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||

	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)))

		reserve_size = max(reserve_size, (uint32_t)280 << 20);

	else if (!reserve_size)

		reserve_size = DISCOVERY_TMR_OFFSET;