Commit 5f70d4ff authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
Browse files

drm/amd/display: Enable DCN clock gating for DCN35 



[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 673d6d73

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+5 −1
Original line number Diff line number Diff line
@@ -291,7 +291,11 @@ 
	type SYMCLKB_FE_SRC_SEL;\

	type SYMCLKC_FE_SRC_SEL;\

	type SYMCLKD_FE_SRC_SEL;\

	type SYMCLKE_FE_SRC_SEL;

	type SYMCLKE_FE_SRC_SEL;\

	type DTBCLK_P0_GATE_DISABLE;\

	type DTBCLK_P1_GATE_DISABLE;\

	type DTBCLK_P2_GATE_DISABLE;\

	type DTBCLK_P3_GATE_DISABLE;\



struct dccg_shift {

	DCCG_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c

+30 −0
Original line number Diff line number Diff line
@@ -256,6 +256,21 @@ static void dccg35_set_dtbclk_dto( 
	if (params->ref_dtbclk_khz && req_dtbclk_khz) {

		uint32_t modulo, phase;



		switch (params->otg_inst) {

		case 0:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);

			break;

		case 1:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);

			break;

		case 2:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);

			break;

		case 3:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);

			break;

		}



		// phase / modulo = dtbclk / dtbclk ref

		modulo = params->ref_dtbclk_khz * 1000;

		phase = req_dtbclk_khz * 1000;
@@ -280,6 +295,21 @@ static void dccg35_set_dtbclk_dto( 
		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

				PIPE_DTO_SRC_SEL[params->otg_inst], 2);

	} else {

		switch (params->otg_inst) {

		case 0:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);

			break;

		case 1:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);

			break;

		case 2:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);

			break;

		case 3:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);

			break;

		}



		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],

				DTBCLK_DTO_ENABLE[params->otg_inst], 0,

				PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h

+6 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#define DCCG_REG_LIST_DCN35() \

	DCCG_REG_LIST_DCN314(),\

	SR(DPPCLK_CTRL),\

	SR(DCCG_GATE_DISABLE_CNTL5),\

	SR(DCCG_GATE_DISABLE_CNTL6),\

	SR(DCCG_GLOBAL_FGCG_REP_CNTL),\

	SR(SYMCLKA_CLOCK_ENABLE),\
@@ -174,7 +175,11 @@ 
	DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\

	DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh)

	DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\



struct dccg *dccg35_create(

		struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c

+1 −9
Original line number Diff line number Diff line
@@ -332,13 +332,6 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) 
	pg_cntl->pg_res_enable[PG_DCIO] = power_on;

}



void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on)

{

	struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);



	REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, power_on ? 1 : 0);

}



static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)

{

	struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
@@ -508,8 +501,7 @@ static const struct pg_cntl_funcs pg_cntl35_funcs = { 
	.mpcc_pg_control = pg_cntl35_mpcc_pg_control,

	.opp_pg_control = pg_cntl35_opp_pg_control,

	.optc_pg_control = pg_cntl35_optc_pg_control,

	.dwb_pg_control = pg_cntl35_dwb_pg_control,

	.set_force_poweron_domain22 = pg_cntl35_set_force_poweron_domain22

	.dwb_pg_control = pg_cntl35_dwb_pg_control

};



struct pg_cntl *pg_cntl35_create(

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h

+0 −1
Original line number Diff line number Diff line
@@ -183,7 +183,6 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl, 
	unsigned int optc_inst, bool power_on);

void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);

void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl);

void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on);



struct pg_cntl *pg_cntl35_create(

	struct dc_context *ctx,