Unverified Commit 5f8456b1 authored by Rob Herring's avatar Rob Herring Committed by Arnd Bergmann
Browse files

arm64: dts: mediatek: Fix "mediatek,merge-mute" and "mediatek,merge-fifo-en" types 



"mediatek,merge-mute" and "mediatek,merge-fifo-en" properties are defined
and used as boolean properties which in DT have no value.

Signed-off-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230830195650.704737-1-robh@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 0bb80ecc

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -2957,7 +2957,7 @@ merge1: vpp-merge@1c10c000 { 
			clock-names = "merge","merge_async";

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;

			mediatek,merge-mute = <1>;

			mediatek,merge-mute;

			resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;

		};
@@ -2970,7 +2970,7 @@ merge2: vpp-merge@1c10d000 { 
			clock-names = "merge","merge_async";

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;

			mediatek,merge-mute = <1>;

			mediatek,merge-mute;

			resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;

		};
@@ -2983,7 +2983,7 @@ merge3: vpp-merge@1c10e000 { 
			clock-names = "merge","merge_async";

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;

			mediatek,merge-mute = <1>;

			mediatek,merge-mute;

			resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;

		};
@@ -2996,7 +2996,7 @@ merge4: vpp-merge@1c10f000 { 
			clock-names = "merge","merge_async";

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;

			mediatek,merge-mute = <1>;

			mediatek,merge-mute;

			resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;

		};
@@ -3009,7 +3009,7 @@ merge5: vpp-merge@1c110000 { 
			clock-names = "merge","merge_async";

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;

			mediatek,merge-fifo-en = <1>;

			mediatek,merge-fifo-en;

			resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;

		};