Commit 5f9e5d20 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'support-one-ptp-device-per-hardware-clock' 

Tariq Toukan says:

====================
Support one PTP device per hardware clock

This series contains two features from Jianbo, followed by simple
cleanups.

Patches 1-9 by Jianbo add support for one PTP device per hardware clock,
described below [1].

Patches 10-12 by Jianbo add support for 200Gbps per-lane link modes in
kernel and mlx5 driver.

Patches 13-15 are simple cleanups by Gal and Carolina.

[1]
PHC (PTP hardware clock) is normally shared by multiple functions
(PF/VF/SF). mlx5 driver currently creates a separate PTP device for each
network interface that shares one PHC.

PHC can be configured to work as free running mode or real time mode.
In this series, only one PTP device is created for the shared PHC when
it is running in real time mode.

To support this feature,
* Firmware needs to support clock identity. When functions share a
  PHC, the clock identities they query are same.
* Driver dynamically allocates mlx5_clock to represent a PHC.
* New devcom component is added for hardware clock. Functions are
  grouped by the identity, and one mlx5_clock is allocated and shared
  by the functions with the same identity.
* When PTP device accesses PHC by its callbacks, the first function
  in the clock devcom list is selected to send commands to firmware.
* PPS IN event is armed on one function. It should be re-armed on
  the other one when current is unloaded.
====================

Link: https://patch.msgid.link/20250203213516.227902-1-tariqt@nvidia.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 3924fa99 689805dc

drivers/net/ethernet/mellanox/mlx5/core/en/port.c

+54 −10
Original line number Diff line number Diff line
@@ -296,11 +296,16 @@ enum mlx5e_fec_supported_link_mode { 
	MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X,

	MLX5E_MAX_FEC_SUPPORTED_LINK_MODE,

};



#define MLX5E_FEC_FIRST_50G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X

#define MLX5E_FEC_FIRST_100G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X

#define MLX5E_FEC_FIRST_200G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X



#define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link)			\

	do {										\
@@ -320,8 +325,10 @@ static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev, 
	return link_mode < MLX5E_FEC_FIRST_50G_PER_LANE_MODE ||

	       (link_mode < MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm)) ||

	       (link_mode >= MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm));

	       (link_mode < MLX5E_FEC_FIRST_200G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm)) ||

	       (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_200G_per_lane_in_pplm));

}



/* get/set FEC admin field for a given speed */
@@ -368,6 +375,18 @@ static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write, 
	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_8x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_1x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_2x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_4x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 1600g_8x);

		break;

	default:

		return -EINVAL;

	}
@@ -421,6 +440,18 @@ static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap, 
	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_8x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_1x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_2x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_4x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 1600g_8x);

		break;

	default:

		return -EINVAL;

	}
@@ -494,6 +525,26 @@ int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active, 
	return 0;

}



static u16 mlx5e_remap_fec_conf_mode(enum mlx5e_fec_supported_link_mode link_mode,

				     u16 conf_fec)

{

	/* RS fec in ethtool is originally mapped to MLX5E_FEC_RS_528_514.

	 * For link modes up to 25G per lane, the value is kept.

	 * For 50G or 100G per lane, it's remapped to MLX5E_FEC_RS_544_514.

	 * For 200G per lane, remapped to MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD.

	 */

	if (conf_fec != BIT(MLX5E_FEC_RS_528_514))

		return conf_fec;



	if (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE)

		return BIT(MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD);



	if (link_mode >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)

		return BIT(MLX5E_FEC_RS_544_514);



	return conf_fec;

}



int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)

{

	bool fec_50g_per_lane = MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm);
@@ -530,14 +581,7 @@ int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy) 
		if (!mlx5e_is_fec_supported_link_mode(dev, i))

			break;



		/* RS fec in ethtool is mapped to MLX5E_FEC_RS_528_514

		 * to link modes up to 25G per lane and to

		 * MLX5E_FEC_RS_544_514 in the new link modes based on

		 * 50G or 100G per lane

		 */

		if (conf_fec == (1 << MLX5E_FEC_RS_528_514) &&

		    i >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)

			conf_fec = (1 << MLX5E_FEC_RS_544_514);

		conf_fec = mlx5e_remap_fec_conf_mode(i, conf_fec);



		mlx5e_get_fec_cap_field(out, &fec_caps, i);

drivers/net/ethernet/mellanox/mlx5/core/en/port.h

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ enum { 
	MLX5E_FEC_NOFEC,

	MLX5E_FEC_FIRECODE,

	MLX5E_FEC_RS_528_514,

	MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD = 4,

	MLX5E_FEC_RS_544_514 = 7,

	MLX5E_FEC_LLRS_272_257_1 = 9,

};

drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c

+2 −2
Original line number Diff line number Diff line
@@ -326,7 +326,7 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix, 
	int node;



	sq->pdev      = c->pdev;

	sq->clock     = &mdev->clock;

	sq->clock     = mdev->clock;

	sq->mkey_be   = c->mkey_be;

	sq->netdev    = c->netdev;

	sq->priv      = c->priv;
@@ -696,7 +696,7 @@ static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params, 
	rq->pdev         = c->pdev;

	rq->netdev       = priv->netdev;

	rq->priv         = priv;

	rq->clock        = &mdev->clock;

	rq->clock        = mdev->clock;

	rq->tstamp       = &priv->tstamp;

	rq->mdev         = mdev;

	rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);

drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h

+0 −5
Original line number Diff line number Diff line
@@ -73,11 +73,6 @@ struct mlx5e_tc_act { 
	bool is_terminating_action;

};



struct mlx5e_tc_flow_action {

	unsigned int num_entries;

	struct flow_action_entry **entries;

};



extern struct mlx5e_tc_act mlx5e_tc_act_drop;

extern struct mlx5e_tc_act mlx5e_tc_act_trap;

extern struct mlx5e_tc_act mlx5e_tc_act_accept;

drivers/net/ethernet/mellanox/mlx5/core/en/trap.c

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ static void mlx5e_init_trap_rq(struct mlx5e_trap *t, struct mlx5e_params *params 
	rq->pdev         = t->pdev;

	rq->netdev       = priv->netdev;

	rq->priv         = priv;

	rq->clock        = &mdev->clock;

	rq->clock        = mdev->clock;

	rq->tstamp       = &priv->tstamp;

	rq->mdev         = mdev;

	rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);