Commit 5fa20ff8 authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe/xe3p_xpc: Treat all PSMI MCR ranges as "INSTANCE0" 



Early versions of the B-spec originally indicated that Xe3p_XPC had two
ranges of PSMI registers requiring MCR steering (one starting at 0xB500,
one starting at 0xB600), and that reads of registers in these ranges
required different grpid values to ensure that a non-terminated value is
obtained.  A late-breaking spec update has simplified this; both ranges
can be safely steered to grpid=0 for reads.

Drop the "PSMI19" replication type and related code, and consolidate
both register ranges into a single entry in the "INSTANCE0" steering
table.

Bspec: 74418
Fixes: be614ea1 ("drm/xe/xe3p_xpc: Add MCR steering")
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20251021224556.437970-2-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 9ea9b457

drivers/gpu/drm/xe/xe_gt_mcr.c

+1 −14
Original line number Diff line number Diff line
@@ -268,13 +268,8 @@ static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = { 
	{},

};



static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {

	{ 0x00B500, 0x00B5FF },

	{},

};



static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {

	{ 0x00B600, 0x00B6FF },		/* PSMI0 */

	{ 0x00B500, 0x00B6FF },		/* PSMI */

	{ 0x00C800, 0x00CFFF },		/* GAMCTRL */

	{ 0x00F000, 0x00F0FF },		/* GAMCTRL */

	{},
@@ -452,12 +447,6 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt) 
	gt->steering[SQIDI_PSMI].instance_target = select & 0x1;

}



static void init_steering_psmi(struct xe_gt *gt)

{

	gt->steering[PSMI19].group_target = 19;

	gt->steering[PSMI19].instance_target = 0;

}



static void init_steering_gam1(struct xe_gt *gt)

{

	gt->steering[GAM1].group_target = 1;
@@ -474,7 +463,6 @@ static const struct { 
	[DSS] =		{ "DSS / XeCore", init_steering_dss },

	[OADDRM] =	{ "OADDRM / GPMXMT", init_steering_oaddrm },

	[SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },

	[PSMI19] =	{ "PSMI[19]",	init_steering_psmi },

	[GAM1] =	{ "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },

	[INSTANCE0] =	{ "INSTANCE 0",	NULL },

	[IMPLICIT_STEERING] = { "IMPLICIT", NULL },
@@ -524,7 +512,6 @@ void xe_gt_mcr_init_early(struct xe_gt *gt) 
			gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;

			gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;

			gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;

			gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;

		} else if (GRAPHICS_VER(xe) >= 20) {

			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;

			gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;

drivers/gpu/drm/xe/xe_gt_types.h

+0 −8
Original line number Diff line number Diff line
@@ -72,14 +72,6 @@ enum xe_steering_type { 
	OADDRM,

	SQIDI_PSMI,



	/*

	 * The bspec lists multiple ranges as "PSMI," but the different

	 * ranges with that label have different grpid steering values so we

	 * treat them independently in code.  Note that the ranges with grpid=0

	 * are included in the INSTANCE0 group above.

	 */

	PSMI19,



	/*

	 * Although most GAM ranges must be steered to (0,0) and thus use the

	 * INSTANCE0 type farther down, some platforms have special rules