Commit 5fa60788 authored by Marek Maslanka's avatar Marek Maslanka Committed by Hans de Goede
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platform/x86:intel/pmc: Revert "Enable the ACPI PM Timer to be turned off when suspended"



Commit e86c8186 ("platform/x86:intel/pmc: Enable the ACPI PM Timer to
be turned off when suspended") can cause the suspend process to hang as
the pmcdev->lock in the pmc_core_acpi_pm_timer_suspend_resume might already
be held by the pmc_core_mphy_pg_show or pmc_core_pll_show if the userspace
gets frozen when these functions are being executed.

Also, pmc_core_acpi_pm_timer_suspend_resume must not sleep, as this
function is called indirectly by the tick_freeze function in
kernel/time/tick-common.c, which holds the spinlock.

Revert the changes for now to fix these issues.

Fixes: e86c8186 ("platform/x86:intel/pmc: Enable the ACPI PM Timer to be turned off when suspended")
Reported-by: default avatarLuca Coelho <luca@coelho.fi>
Closes: https://lore.kernel.org/lkml/40555604c3f4be43bf72e72d5409eaece4be9320.camel@coelho.fi/


Signed-off-by: default avatarMarek Maslanka <mmaslanka@google.com>
Link: https://lore.kernel.org/r/20241012182656.2107178-1-mmaslanka@google.com


Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 2fae3129
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+0 −2
Original line number Diff line number Diff line
@@ -295,8 +295,6 @@ const struct pmc_reg_map adl_reg_map = {
	.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
	.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
	.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
	.lpm_num_modes = ADL_LPM_NUM_MODES,
	.lpm_num_maps = ADL_LPM_NUM_MAPS,
+0 −2
Original line number Diff line number Diff line
@@ -200,8 +200,6 @@ const struct pmc_reg_map cnp_reg_map = {
	.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
	.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
	.ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
	.etr3_offset = ETR3_OFFSET,
};
+0 −46
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/acpi_pmtmr.h>
#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
@@ -1258,39 +1257,6 @@ static bool pmc_core_is_pson_residency_enabled(struct pmc_dev *pmcdev)
	return val == 1;
}

/*
 * Enable or disable ACPI PM Timer
 *
 * This function is intended to be a callback for ACPI PM suspend/resume event.
 * The ACPI PM Timer is enabled on resume only if it was enabled during suspend.
 */
static void pmc_core_acpi_pm_timer_suspend_resume(void *data, bool suspend)
{
	struct pmc_dev *pmcdev = data;
	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
	const struct pmc_reg_map *map = pmc->map;
	bool enabled;
	u32 reg;

	if (!map->acpi_pm_tmr_ctl_offset)
		return;

	guard(mutex)(&pmcdev->lock);

	if (!suspend && !pmcdev->enable_acpi_pm_timer_on_resume)
		return;

	reg = pmc_core_reg_read(pmc, map->acpi_pm_tmr_ctl_offset);
	enabled = !(reg & map->acpi_pm_tmr_disable_bit);
	if (suspend)
		reg |= map->acpi_pm_tmr_disable_bit;
	else
		reg &= ~map->acpi_pm_tmr_disable_bit;
	pmc_core_reg_write(pmc, map->acpi_pm_tmr_ctl_offset, reg);

	pmcdev->enable_acpi_pm_timer_on_resume = suspend && enabled;
}

static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
	debugfs_remove_recursive(pmcdev->dbgfs_dir);
@@ -1486,7 +1452,6 @@ static int pmc_core_probe(struct platform_device *pdev)
	struct pmc_dev *pmcdev;
	const struct x86_cpu_id *cpu_id;
	int (*core_init)(struct pmc_dev *pmcdev);
	const struct pmc_reg_map *map;
	struct pmc *primary_pmc;
	int ret;

@@ -1545,11 +1510,6 @@ static int pmc_core_probe(struct platform_device *pdev)
	pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) *
			       pmc_core_adjust_slp_s0_step(primary_pmc, 1));

	map = primary_pmc->map;
	if (map->acpi_pm_tmr_ctl_offset)
		acpi_pmtmr_register_suspend_resume_callback(pmc_core_acpi_pm_timer_suspend_resume,
							 pmcdev);

	device_initialized = true;
	dev_info(&pdev->dev, " initialized\n");

@@ -1559,12 +1519,6 @@ static int pmc_core_probe(struct platform_device *pdev)
static void pmc_core_remove(struct platform_device *pdev)
{
	struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
	const struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
	const struct pmc_reg_map *map = pmc->map;

	if (map->acpi_pm_tmr_ctl_offset)
		acpi_pmtmr_unregister_suspend_resume_callback();

	pmc_core_dbgfs_unregister(pmcdev);
	pmc_core_clean_structure(pdev);
}
+0 −8
Original line number Diff line number Diff line
@@ -68,8 +68,6 @@ struct telem_endpoint;
#define SPT_PMC_LTR_SCC				0x3A0
#define SPT_PMC_LTR_ISH				0x3A4

#define SPT_PMC_ACPI_PM_TMR_CTL_OFFSET		0x18FC

/* Sunrise Point: PGD PFET Enable Ack Status Registers */
enum ppfear_regs {
	SPT_PMC_XRAM_PPFEAR0A = 0x590,
@@ -150,8 +148,6 @@ enum ppfear_regs {
#define SPT_PMC_VRIC1_SLPS0LVEN			BIT(13)
#define SPT_PMC_VRIC1_XTALSDQDIS		BIT(22)

#define SPT_PMC_BIT_ACPI_PM_TMR_DISABLE		BIT(1)

/* Cannonlake Power Management Controller register offsets */
#define CNP_PMC_SLPS0_DBG_OFFSET		0x10B4
#define CNP_PMC_PM_CFG_OFFSET			0x1818
@@ -355,8 +351,6 @@ struct pmc_reg_map {
	const u8  *lpm_reg_index;
	const u32 pson_residency_offset;
	const u32 pson_residency_counter_step;
	const u32 acpi_pm_tmr_ctl_offset;
	const u32 acpi_pm_tmr_disable_bit;
};

/**
@@ -432,8 +426,6 @@ struct pmc_dev {
	u32 die_c6_offset;
	struct telem_endpoint *punit_ep;
	struct pmc_info *regmap_list;

	bool enable_acpi_pm_timer_on_resume;
};

enum pmc_index {
+0 −2
Original line number Diff line number Diff line
@@ -46,8 +46,6 @@ const struct pmc_reg_map icl_reg_map = {
	.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
	.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
	.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
	.etr3_offset = ETR3_OFFSET,
};
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