Commit 5fad7d8c authored by Max Tseng's avatar Max Tseng Committed by Alex Deucher
Browse files

drm/amd/display: augment display clock in dc_cap structure



[Why]
Allow dc report maximum display clock possible at vmin

Reviewed-by: default avatarWayne Lin <wayne.lin@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarMax Tseng <max.tseng@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b308e6f3
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+1 −0
Original line number Diff line number Diff line
@@ -270,6 +270,7 @@ struct dc_caps {
	uint16_t subvp_vertical_int_margin_us;
	bool seamless_odm;
	uint32_t max_v_total;
	uint32_t max_disp_clock_khz_at_vmin;
	uint8_t subvp_drr_vblank_start_margin_us;
};

+2 −0
Original line number Diff line number Diff line
@@ -1914,6 +1914,8 @@ static bool dcn314_resource_construct(
	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
	dc->caps.color.mpc.ocsc = 1;

	dc->caps.max_disp_clock_khz_at_vmin = 694000;

	/* Use pipe context based otg sync logic */
	dc->config.use_pipe_ctx_sync_logic = true;

+2 −0
Original line number Diff line number Diff line
@@ -1832,6 +1832,8 @@ static bool dcn35_resource_construct(
	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
	dc->caps.color.mpc.ocsc = 1;

	dc->caps.max_disp_clock_khz_at_vmin = 669154;

	/* Use pipe context based otg sync logic */
	dc->config.use_pipe_ctx_sync_logic = true;
	/* read VBIOS LTTPR caps */