Commit 5fcccba1 authored by Gowthami Thiagarajan's avatar Gowthami Thiagarajan Committed by Will Deacon
Browse files

perf/marvell: Odyssey LLC-TAD performance monitor support 



Each TAD provides eight 64-bit counters for monitoring
cache behavior.The driver always configures the same counter for
all the TADs. The user would end up effectively reserving one of
eight counters in every TAD to look across all TADs.
The occurrences of events are aggregated and presented to the user
at the end of running the workload. The driver does not provide a
way for the user to partition TADs so that different TADs are used for
different applications.

The performance events reflect various internal or interface activities.
By combining the values from multiple performance counters, cache
performance can be measured in terms such as: cache miss rate, cache
allocations, interface retry rate, internal resource occupancy, etc.

Each supported counter's event and formatting information is exposed
to sysfs at /sys/devices/tad/. Use perf tool stat command to measure
the pmu events. For instance:

perf stat -e tad_hit_ltg,tad_hit_dtg <workload>

Signed-off-by: default avatarGowthami Thiagarajan <gthiagarajan@marvell.com>
Link: https://lore.kernel.org/r/20241108040619.753343-6-gthiagarajan@marvell.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 59731e23

Documentation/admin-guide/perf/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Performance monitor support 
   qcom_l3_pmu

   starfive_starlink_pmu

   mrvl-odyssey-ddr-pmu

   mrvl-odyssey-tad-pmu

   arm-ccn

   arm-cmn

   arm-ni

Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst

0 → 100644
+37 −0
Original line number Diff line number Diff line 
====================================================================

Marvell Odyssey LLC-TAD Performance Monitoring Unit (PMU UNCORE)

====================================================================



Each TAD provides eight 64-bit counters for monitoring

cache behavior.The driver always configures the same counter for

all the TADs. The user would end up effectively reserving one of

eight counters in every TAD to look across all TADs.

The occurrences of events are aggregated and presented to the user

at the end of running the workload. The driver does not provide a

way for the user to partition TADs so that different TADs are used for

different applications.



The performance events reflect various internal or interface activities.

By combining the values from multiple performance counters, cache

performance can be measured in terms such as: cache miss rate, cache

allocations, interface retry rate, internal resource occupancy, etc.



The PMU driver exposes the available events and format options under sysfs::



        /sys/bus/event_source/devices/tad/events/

        /sys/bus/event_source/devices/tad/format/



Examples::



   $ perf list | grep tad

        tad/tad_alloc_any/                                 [Kernel PMU event]

        tad/tad_alloc_dtg/                                 [Kernel PMU event]

        tad/tad_alloc_ltg/                                 [Kernel PMU event]

        tad/tad_hit_any/                                   [Kernel PMU event]

        tad/tad_hit_dtg/                                   [Kernel PMU event]

        tad/tad_hit_ltg/                                   [Kernel PMU event]

        tad/tad_req_msh_in_exlmn/                          [Kernel PMU event]

        tad/tad_tag_rd/                                    [Kernel PMU event]

        tad/tad_tot_cycle/                                 [Kernel PMU event]



   $ perf stat -e tad_alloc_dtg,tad_alloc_ltg,tad_alloc_any,tad_hit_dtg,tad_hit_ltg,tad_hit_any,tad_tag_rd <workload>

drivers/perf/marvell_cn10k_tad_pmu.c

+35 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct tad_pmu { 


enum mrvl_tad_pmu_version {

	TAD_PMU_V1 = 1,

	TAD_PMU_V2,

};



struct tad_pmu_data {
@@ -222,6 +223,24 @@ static const struct attribute_group tad_pmu_events_attr_group = { 
	.attrs = tad_pmu_event_attrs,

};



static struct attribute *ody_tad_pmu_event_attrs[] = {

	TAD_PMU_EVENT_ATTR(tad_req_msh_in_exlmn, 0x3),

	TAD_PMU_EVENT_ATTR(tad_alloc_dtg, 0x1a),

	TAD_PMU_EVENT_ATTR(tad_alloc_ltg, 0x1b),

	TAD_PMU_EVENT_ATTR(tad_alloc_any, 0x1c),

	TAD_PMU_EVENT_ATTR(tad_hit_dtg, 0x1d),

	TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e),

	TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f),

	TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20),

	TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xFF),

	NULL

};



static const struct attribute_group ody_tad_pmu_events_attr_group = {

	.name = "events",

	.attrs = ody_tad_pmu_event_attrs,

};



PMU_FORMAT_ATTR(event, "config:0-7");



static struct attribute *tad_pmu_format_attrs[] = {
@@ -260,6 +279,13 @@ static const struct attribute_group *tad_pmu_attr_groups[] = { 
	NULL

};



static const struct attribute_group *ody_tad_pmu_attr_groups[] = {

	&ody_tad_pmu_events_attr_group,

	&tad_pmu_format_attr_group,

	&tad_pmu_cpumask_attr_group,

	NULL

};



static int tad_pmu_probe(struct platform_device *pdev)

{

	const struct tad_pmu_data *dev_data;
@@ -350,6 +376,8 @@ static int tad_pmu_probe(struct platform_device *pdev) 


	if (version == TAD_PMU_V1)

		tad_pmu->pmu.attr_groups = tad_pmu_attr_groups;

	else

		tad_pmu->pmu.attr_groups = ody_tad_pmu_attr_groups;



	tad_pmu->cpu = raw_smp_processor_id();
@@ -385,6 +413,12 @@ static const struct tad_pmu_data tad_pmu_data = { 
};

#endif



#ifdef CONFIG_ACPI

static const struct tad_pmu_data tad_pmu_v2_data = {

	.id   = TAD_PMU_V2,

};

#endif



#ifdef CONFIG_OF

static const struct of_device_id tad_pmu_of_match[] = {

	{ .compatible = "marvell,cn10k-tad-pmu", .data = &tad_pmu_data },
@@ -395,6 +429,7 @@ static const struct of_device_id tad_pmu_of_match[] = { 
#ifdef CONFIG_ACPI

static const struct acpi_device_id tad_pmu_acpi_match[] = {

	{"MRVL000B", (kernel_ulong_t)&tad_pmu_data},

	{"MRVL000D", (kernel_ulong_t)&tad_pmu_v2_data},

	{},

};

MODULE_DEVICE_TABLE(acpi, tad_pmu_acpi_match);