Commit 5fd95dab authored by Dr. David Alan Gilbert's avatar Dr. David Alan Gilbert Committed by Alex Deucher
Browse files

drm/amd/display: Remove last parts of timing_trace 



Commit c2c2ce1e ("drm/amd/display: Optimize passive update planes.")
removed the last caller of context_timing_trace.
Remove it.

With that gone, no one is now looking at the 'timing_trace' flag, remove
it and all the places that set it.

Signed-off-by: default avatarDr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8b89acc0

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

+0 −42
Original line number Diff line number Diff line
@@ -46,11 +46,6 @@ 
			DC_LOG_IF_TRACE(__VA_ARGS__); \

} while (0)



#define TIMING_TRACE(...) do {\

	if (dc->debug.timing_trace) \

		DC_LOG_SYNC(__VA_ARGS__); \

} while (0)



#define CLOCK_TRACE(...) do {\

	if (dc->debug.clock_trace) \

		DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
@@ -306,43 +301,6 @@ void post_surface_trace(struct dc *dc) 


}



void context_timing_trace(

		struct dc *dc,

		struct resource_context *res_ctx)

{

	int i;

	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};

	struct crtc_position position;

	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

	DC_LOGGER_INIT(dc->ctx->logger);





	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

		/* get_position() returns CRTC vertical/horizontal counter

		 * hence not applicable for underlay pipe

		 */

		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)

			continue;



		pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);

		h_pos[i] = position.horizontal_count;

		v_pos[i] = position.vertical_count;

	}

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];



		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)

			continue;



		TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  V_pos:%d\n",

				pipe_ctx->stream_res.tg->inst,

				pipe_ctx->stream->timing.h_total,

				pipe_ctx->stream->timing.v_total,

				h_pos[i], v_pos[i]);

	}

}



void context_clock_trace(

		struct dc *dc,

		struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dc.h

+0 −1
Original line number Diff line number Diff line
@@ -868,7 +868,6 @@ struct dc_debug_options { 
	bool sanity_checks;

	bool max_disp_clk;

	bool surface_trace;

	bool timing_trace;

	bool clock_trace;

	bool validation_trace;

	bool bandwidth_calcs_trace;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

+0 −2
Original line number Diff line number Diff line
@@ -533,7 +533,6 @@ static const struct dc_debug_options debug_defaults_drv = { 
		.sanity_checks = true,

		.disable_dmcu = false,

		.force_abm_enable = false,

		.timing_trace = false,

		.clock_trace = true,



		/* raven smu dones't allow 0 disp clk,
@@ -563,7 +562,6 @@ static const struct dc_debug_options debug_defaults_drv = { 
static const struct dc_debug_options debug_defaults_diags = {

		.disable_dmcu = false,

		.force_abm_enable = false,

		.timing_trace = true,

		.clock_trace = true,

		.disable_stutter = true,

		.disable_pplib_clock_request = true,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

+0 −1
Original line number Diff line number Diff line
@@ -706,7 +706,6 @@ static const struct resource_caps res_cap_nv14 = { 
static const struct dc_debug_options debug_defaults_drv = {

		.disable_dmcu = false,

		.force_abm_enable = false,

		.timing_trace = false,

		.clock_trace = true,

		.disable_pplib_clock_request = true,

		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

+0 −1
Original line number Diff line number Diff line
@@ -600,7 +600,6 @@ static const struct dc_plane_cap plane_cap = { 
static const struct dc_debug_options debug_defaults_drv = {

		.disable_dmcu = true,

		.force_abm_enable = false,

		.timing_trace = false,

		.clock_trace = true,

		.disable_pplib_clock_request = true,

		.pipe_split_policy = MPC_SPLIT_DYNAMIC,