Commit 5fddf9ab authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: Add ESR_ELx_FSC_ADDRSZ_L() helper 



Although we have helpers that encode the level of a given fault
type, the Address Size fault type is missing it.

While we're at it, fix the bracketting for ESR_ELx_FSC_ACCESS_L()
and ESR_ELx_FSC_PERM_L().

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent b229b46b

arch/arm64/include/asm/esr.h

+3 −2
Original line number Diff line number Diff line
@@ -122,8 +122,8 @@ 
#define ESR_ELx_FSC_SECC_TTW(n)	(0x1c + (n))



/* Status codes for individual page table levels */

#define ESR_ELx_FSC_ACCESS_L(n)	(ESR_ELx_FSC_ACCESS + n)

#define ESR_ELx_FSC_PERM_L(n)	(ESR_ELx_FSC_PERM + n)

#define ESR_ELx_FSC_ACCESS_L(n)	(ESR_ELx_FSC_ACCESS + (n))

#define ESR_ELx_FSC_PERM_L(n)	(ESR_ELx_FSC_PERM + (n))



#define ESR_ELx_FSC_FAULT_nL	(0x2C)

#define ESR_ELx_FSC_FAULT_L(n)	(((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
@@ -161,6 +161,7 @@ 


/* ISS field definitions for exceptions taken in to Hyp */

#define ESR_ELx_FSC_ADDRSZ	(0x00)

#define ESR_ELx_FSC_ADDRSZ_L(n)	(ESR_ELx_FSC_ADDRSZ + (n))

#define ESR_ELx_CV		(UL(1) << 24)

#define ESR_ELx_COND_SHIFT	(20)

#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)