Commit 5fde104e authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by Andi Shyti
Browse files

drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 



This bit does not cause an explicit L3 flush. We already use
PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.

v2: Use FLUSH_L3 only pre-MTL since spec will likely remain
the same going forward.

Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Acked-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231017195309.2476088-1-vinay.belgaumkar@intel.com
parent f1cdb599

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+5 −2
Original line number Diff line number Diff line
@@ -278,7 +278,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 
		 * deals with Protected Memory which is not needed for

		 * AUX CCS invalidation and lead to unwanted side effects.

		 */

		if (mode & EMIT_FLUSH)

		if ((mode & EMIT_FLUSH) &&

		    GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))

			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
@@ -812,12 +813,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
	u32 flags = (PIPE_CONTROL_CS_STALL |

		     PIPE_CONTROL_TLB_INVALIDATE |

		     PIPE_CONTROL_TILE_CACHE_FLUSH |

		     PIPE_CONTROL_FLUSH_L3 |

		     PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

		     PIPE_CONTROL_DEPTH_CACHE_FLUSH |

		     PIPE_CONTROL_DC_FLUSH_ENABLE |

		     PIPE_CONTROL_FLUSH_ENABLE);



	if (GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))

		flags |= PIPE_CONTROL_FLUSH_L3;



	/* Wa_14016712196 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))

		/* dummy PIPE_CONTROL + depth flush */