Commit 602ffd4c authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/mm' into for-next/core 

* for-next/mm:
  arm64: mm: Test for pmd_sect() in vmemmap_check_pmd()
  arm64/mm: Replace open encodings with PXD_TABLE_BIT
  arm64/mm: Rename pte_mkpresent() as pte_mkvalid()
  arm64: Kconfig: force ARM64_PAN=y when enabling TTBR0 sw PAN
  arm64/kvm: Avoid invalid physical addresses to signal owner updates
  arm64/kvm: Configure HYP TCR.PS/DS based on host stage1
  arm64/mm: Override PARange for !LPA2 and use it consistently
  arm64/mm: Reduce PA space to 48 bits when LPA2 is not enabled
parents 6e117330 9ab2601d

arch/arm64/Kconfig

+2 −4
Original line number Diff line number Diff line
@@ -1379,7 +1379,6 @@ config ARM64_VA_BITS_48 


config ARM64_VA_BITS_52

	bool "52-bit"

	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN

	help

	  Enable 52-bit virtual addressing for userspace when explicitly

	  requested via a hint to mmap(). The kernel will also use 52-bit
@@ -1431,7 +1430,6 @@ config ARM64_PA_BITS_48 
config ARM64_PA_BITS_52

	bool "52-bit"

	depends on ARM64_64K_PAGES || ARM64_VA_BITS_52

	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN

	help

	  Enable support for a 52-bit physical address space, introduced as

	  part of the ARMv8.2-LPA extension.
@@ -1681,6 +1679,7 @@ config RODATA_FULL_DEFAULT_ENABLED 
config ARM64_SW_TTBR0_PAN

	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"

	depends on !KCSAN

	select ARM64_PAN

	help

	  Enabling this option prevents the kernel from accessing

	  user-space memory directly by pointing TTBR0_EL1 to a reserved
@@ -1937,7 +1936,6 @@ config ARM64_RAS_EXTN 
config ARM64_CNP

	bool "Enable support for Common Not Private (CNP) translations"

	default y

	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN

	help

	  Common Not Private (CNP) allows translation table entries to

	  be shared between different PEs in the same inner shareable
@@ -2132,7 +2130,7 @@ config ARM64_MTE 
	depends on AS_HAS_ARMV8_5

	depends on AS_HAS_LSE_ATOMICS

	# Required for tag checking in the uaccess routines

	depends on ARM64_PAN

	select ARM64_PAN

	select ARCH_HAS_SUBPAGE_FAULTS

	select ARCH_USES_HIGH_VMA_FLAGS

	select ARCH_USES_PG_ARCH_2

arch/arm64/include/asm/assembler.h

+5 −0
Original line number Diff line number Diff line
@@ -343,6 +343,11 @@ alternative_cb_end 
	// Narrow PARange to fit the PS field in TCR_ELx

	ubfx	\tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3

	mov	\tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX

#ifdef CONFIG_ARM64_LPA2

alternative_if_not ARM64_HAS_VA52

	mov	\tmp1, #ID_AA64MMFR0_EL1_PARANGE_48

alternative_else_nop_endif

#endif

	cmp	\tmp0, \tmp1

	csel	\tmp0, \tmp1, \tmp0, hi

	bfi	\tcr, \tmp0, \pos, #3

arch/arm64/include/asm/pgtable-hwdef.h

+0 −6
Original line number Diff line number Diff line
@@ -222,12 +222,6 @@ 
 */

#define S1_TABLE_AP		(_AT(pmdval_t, 3) << 61)



/*

 * Highest possible physical address supported.

 */

#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)

#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)



#define TTBR_CNP_BIT		(UL(1) << 0)



/*

arch/arm64/include/asm/pgtable-prot.h

+7 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ extern unsigned long prot_ns_shared; 
#define lpa2_is_enabled()	false

#define PTE_MAYBE_SHARED	PTE_SHARED

#define PMD_MAYBE_SHARED	PMD_SECT_S

#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)

#else

static inline bool __pure lpa2_is_enabled(void)

{
@@ -89,8 +90,14 @@ static inline bool __pure lpa2_is_enabled(void) 


#define PTE_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PTE_SHARED)

#define PMD_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PMD_SECT_S)

#define PHYS_MASK_SHIFT		(lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)

#endif



/*

 * Highest possible physical address supported.

 */

#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)



/*

 * If we have userspace only BTI we don't want to mark kernel pages

 * guarded even if the system does support BTI.

arch/arm64/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -273,7 +273,7 @@ static inline pte_t pte_mknoncont(pte_t pte) 
	return clear_pte_bit(pte, __pgprot(PTE_CONT));

}



static inline pte_t pte_mkpresent(pte_t pte)

static inline pte_t pte_mkvalid(pte_t pte)

{

	return set_pte_bit(pte, __pgprot(PTE_VALID));

}