Commit 607a9afa authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Mathieu Poirier
Browse files

arm64: errata: Add detection for TRBE ignored system register writes 



TRBE implementations affected by Arm erratum #2064142 might fail to write
into certain system registers after the TRBE has been disabled. Under some
conditions after TRBE has been disabled, writes into certain TRBE registers
TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be
ignored and not be effected. This adds a new errata ARM64_ERRATUM_2064142
in arm64 errata framework.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1643120437-14352-3-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent 53960faf

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ stable kernels. 
| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2064142        | ARM64_ERRATUM_2064142       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

arch/arm64/Kconfig

+18 −0
Original line number Diff line number Diff line
@@ -778,6 +778,24 @@ config ARM64_ERRATUM_2224489 


	  If unsure, say Y.



config ARM64_ERRATUM_2064142

	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.



	  Affected Cortex-A510 core might fail to write into system registers after the

	  TRBE has been disabled. Under some conditions after the TRBE has been disabled

	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,

	  and TRBTRG_EL1 will be ignored and will not be effected.



	  Work around this in the driver by executing TSB CSYNC and DSB after collection

	  is stopped and before performing a system register write to one of the affected

	  registers.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/kernel/cpu_errata.c

+9 −0
Original line number Diff line number Diff line
@@ -597,6 +597,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,

		CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2064142

	{

		.desc = "ARM erratum 2064142",

		.capability = ARM64_WORKAROUND_2064142,



		/* Cortex-A510 r0p0 - r0p2 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)

	},

#endif

	{

	}

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ WORKAROUND_1418040 
WORKAROUND_1463225

WORKAROUND_1508412

WORKAROUND_1542419

WORKAROUND_2064142

WORKAROUND_TRBE_OVERWRITE_FILL_MODE

WORKAROUND_TSB_FLUSH_FAILURE

WORKAROUND_TRBE_WRITE_OUT_OF_RANGE