Commit 60821fb4 authored by Yong-Xuan Wang's avatar Yong-Xuan Wang Committed by Anup Patel
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RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation 



In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:

"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectified input value is
low, when the interrupt is forwarded by MSI, or by a relevant
write to an in_clrip register or to clripnum."

Update the aplic_write_pending() to match the spec.

Fixes: d8dd9f11 ("RISC-V: KVM: Fix APLIC setipnum_le/be write emulation")
Signed-off-by: default avatarYong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: default avatarVincent Chen <vincent.chen@sifive.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20241029085542.30541-1-yongxuan.wang@sifive.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 5bdecd89

arch/riscv/kvm/aia_aplic.c

+2 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending) 
	if (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH ||

	    sm == APLIC_SOURCECFG_SM_LEVEL_LOW) {

		if (!pending)

			goto skip_write_pending;

			goto noskip_write_pending;

		if ((irqd->state & APLIC_IRQ_STATE_INPUT) &&

		    sm == APLIC_SOURCECFG_SM_LEVEL_LOW)

			goto skip_write_pending;
@@ -152,6 +152,7 @@ static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending) 
			goto skip_write_pending;

	}



noskip_write_pending:

	if (pending)

		irqd->state |= APLIC_IRQ_STATE_PENDING;

	else