Commit 60a4e18e authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
Browse files

drm/msm/adreno: Do CX GBIF config before GMU start 



GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF
configurations before GMU wakes up. This was not a problem so far, but
A840 GPU is very sensitive to this requirement. Also, move these
registers to the catalog.

Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689024/


Message-ID: <20251118-kaana-gpu-support-v4-17-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 0700b9f6

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+32 −0
Original line number Diff line number Diff line
@@ -672,6 +672,14 @@ static const u32 a690_protect_regs[] = { 
};

DECLARE_ADRENO_PROTECT(a690_protect, 48);



static const struct adreno_reglist a640_gbif[] = {

	{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 },

	{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 },

	{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 },

	{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 },

	{ },

};



static const struct adreno_info a6xx_gpus[] = {

	{

		.chip_ids = ADRENO_CHIP_IDS(0x06010000),
@@ -688,6 +696,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a612_hwcg,

			.protect = &a630_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020202,

			.prim_fifo_threshold = 0x00080000,

		},
@@ -894,6 +903,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a620_hwcg,

			.protect = &a650_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020200,

			.prim_fifo_threshold = 0x00010000,

		},
@@ -916,6 +926,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a690_hwcg,

			.protect = &a650_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020200,

			.prim_fifo_threshold = 0x00010000,

			.bcms = (const struct a6xx_bcm[]) {
@@ -998,6 +1009,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a650_hwcg,

			.protect = &a650_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020202,

			.prim_fifo_threshold = 0x00300200,

		},
@@ -1024,6 +1036,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a660_hwcg,

			.protect = &a660_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020000,

			.prim_fifo_threshold = 0x00300200,

		},
@@ -1042,6 +1055,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a690_hwcg,

			.protect = &a660_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020200,

			.prim_fifo_threshold = 0x00300200,

		},
@@ -1066,6 +1080,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a660_hwcg,

			.protect = &a660_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020202,

			.prim_fifo_threshold = 0x00200200,

		},
@@ -1112,6 +1127,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a690_hwcg,

			.protect = &a690_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020200,

			.prim_fifo_threshold = 0x00800200,

		},
@@ -1447,6 +1463,7 @@ static const struct adreno_info a7xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a702_hwcg,

			.protect = &a650_protect,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020202,

			.prim_fifo_threshold = 0x0000c000,

		},
@@ -1474,6 +1491,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a730_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.gbif_cx = a640_gbif,

			.gmu_cgc_mode = 0x00020000,

		},

		.preempt_record_size = 2860 * SZ_1K,
@@ -1495,6 +1513,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a740_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x7020100,

			.gmu_cgc_mode = 0x00020202,

			.bcms = (const struct a6xx_bcm[]) {
@@ -1529,6 +1548,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.ifpc_reglist = &a750_ifpc_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x7050001,

			.gmu_cgc_mode = 0x00020202,

			.bcms = (const struct a6xx_bcm[]) {
@@ -1570,6 +1590,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.ifpc_reglist = &a750_ifpc_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x7090100,

			.gmu_cgc_mode = 0x00020202,

			.bcms = (const struct a6xx_bcm[]) {
@@ -1602,6 +1623,7 @@ static const struct adreno_info a7xx_gpus[] = { 
			.hwcg = a740_hwcg,

			.protect = &a730_protect,

			.pwrup_reglist = &a7xx_pwrup_reglist,

			.gbif_cx = a640_gbif,

			.gmu_chipid = 0x70f0000,

			.gmu_cgc_mode = 0x00020222,

			.bcms = (const struct a6xx_bcm[]) {
@@ -1749,6 +1771,15 @@ static const u32 a840_protect_regs[] = { 
};

DECLARE_ADRENO_PROTECT(a840_protect, 15);



static const struct adreno_reglist a840_gbif[] = {

	{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },

	{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },

	{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },

	{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },

	{ REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },

	{ },

};



static const struct adreno_info a8xx_gpus[] = {

	{

		.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
@@ -1766,6 +1797,7 @@ static const struct adreno_info a8xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.protect = &a840_protect,

			.nonctxt_reglist = a840_nonctxt_regs,

			.gbif_cx = a840_gbif,

			.max_slices = 3,

			.gmu_chipid = 0x8020100,

			.bcms = (const struct a6xx_bcm[]) {

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+11 −0
Original line number Diff line number Diff line
@@ -894,7 +894,9 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 
{

	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

	struct msm_gpu *gpu = &adreno_gpu->base;

	const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx;

	const struct adreno_reglist *gbif_cx = a6xx_info->gbif_cx;

	u32 fence_range_lower, fence_range_upper;

	u32 chipid = 0;

	int ret;
@@ -990,6 +992,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 
			  gmu->log.iova | (gmu->log.size / SZ_4K - 1));

	}



	/* For A7x and newer, do the CX GBIF configurations before GMU wake up */

	for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++)

		gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value);



	if (adreno_is_a8xx(adreno_gpu)) {

		gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);

		gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);

	}



	/* Set up the lowest idle level on the GMU */

	a6xx_gmu_power_config(gmu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+10 −7
Original line number Diff line number Diff line
@@ -1279,17 +1279,20 @@ static int hw_init(struct msm_gpu *gpu) 
	/* enable hardware clockgating */

	a6xx_set_hwcg(gpu, true);



	/* VBIF/GBIF start*/

	if (adreno_is_a610_family(adreno_gpu) ||

	    adreno_is_a640_family(adreno_gpu) ||

	    adreno_is_a650_family(adreno_gpu) ||

	    adreno_is_a7xx(adreno_gpu)) {

	/* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */

	if (adreno_is_a610_family(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);

		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,

			  adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3);

	}



	if (adreno_is_a610_family(adreno_gpu) ||

	    adreno_is_a640_family(adreno_gpu) ||

	    adreno_is_a650_family(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);

	} else if (adreno_is_a7xx(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212);

	} else {

		gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);

	}

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ struct a6xx_info { 
	const struct adreno_protect *protect;

	const struct adreno_reglist_list *pwrup_reglist;

	const struct adreno_reglist_list *ifpc_reglist;

	const struct adreno_reglist *gbif_cx;

	const struct adreno_reglist_pipe *nonctxt_reglist;

	u32 max_slices;

	u32 gmu_chipid;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

+0 −7
Original line number Diff line number Diff line
@@ -519,13 +519,6 @@ static int hw_init(struct msm_gpu *gpu) 
	gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000);

	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);



	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);

	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);

	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);

	gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);

	gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);

	gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);



	/* Make all blocks contribute to the GPU BUSY perf counter */

	gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);