Commit 60b8d3a2 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Dmitry Baryshkov
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dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc path 



There's a separate path that allows register access from CPUSS.
Describe it.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/641464/
Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-2-0c84aceb0ef9@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent 98a8920e

Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

+5 −1
Original line number Diff line number Diff line
@@ -38,12 +38,16 @@ properties: 
    maxItems: 1



  interconnects:

    maxItems: 2

    items:

      - description: Interconnect path from the MDP0 port to the data bus

      - description: Interconnect path from the MDP1 port to the data bus

      - description: Interconnect path from the CPU to the reg bus



  interconnect-names:

    items:

      - const: mdp0-mem

      - const: mdp1-mem

      - const: cpu-cfg



patternProperties:

  "^display-controller@[0-9a-f]+$":