Commit 60fcdf64 authored by Matt Roper's avatar Matt Roper Committed by Gustavo Sousa
Browse files

drm/xe/xe3p_lpg: Extend 'group ID' mask size 



Xe3p_LPG extends the 'group ID' register mask by one bit.  Since the new
upper bit (12) was unused on previous platforms, we can safely extend
the existing mask size without worrying about adding conditional version
checks to the register programming.

Bspec: 67175
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patch.msgid.link/20260206-nvl-p-upstreaming-v3-9-636e1ad32688@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
parent ce0e1a63

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ 
#define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)

#define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)

#define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)

#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)

#define   MTL_MCR_GROUPID			REG_GENMASK(12, 8)

#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)



#define PS_INVOCATION_COUNT			XE_REG(0x2348)