Commit 614106a7 authored by Ulf Hansson's avatar Ulf Hansson
Browse files

pmdomain: Merge branch dt into next 



Merge the immutable branch dt into next, to allow the DT bindings to be
tested together with changes that are targeted for v6.18.

Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parents 5c479a67 5bcf9e1d

Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml

+24 −6
Original line number Diff line number Diff line
@@ -19,11 +19,14 @@ description: | 


properties:

  compatible:

    enum:

    oneOf:

      - enum:

          - marvell,pxa1908-apbc

          - marvell,pxa1908-apbcp

          - marvell,pxa1908-mpmu

      - marvell,pxa1908-apmu

      - items:

          - const: marvell,pxa1908-apmu

          - const: syscon



  reg:

    maxItems: 1
@@ -31,6 +34,9 @@ properties: 
  '#clock-cells':

    const: 1



  '#power-domain-cells':

    const: 1



required:

  - compatible

  - reg
@@ -38,11 +44,23 @@ required: 


additionalProperties: false



if:

  not:

    properties:

      compatible:

        contains:

          const: marvell,pxa1908-apmu



then:

  properties:

    '#power-domain-cells': false



examples:

  # APMU block:

  - |

    clock-controller@d4282800 {

      compatible = "marvell,pxa1908-apmu";

      compatible = "marvell,pxa1908-apmu", "syscon";

      reg = <0xd4282800 0x400>;

      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -2872,6 +2872,7 @@ S: Maintained 
F:	arch/arm64/boot/dts/marvell/mmp/

F:	drivers/clk/mmp/clk-pxa1908*.c

F:	include/dt-bindings/clock/marvell,pxa1908.h

F:	include/dt-bindings/power/marvell,pxa1908-power.h









ARM/Mediatek RTC DRIVER









M:	Eddie Huang <eddie.huang@mediatek.com>
































include/dt-bindings/power/marvell,pxa1908-power.h
0 → 100644



+17
−0






























Original line number
Diff line number
Diff line









/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */









/*









 * Marvell PXA1908 power domains









 *









 * Copyright 2025, Duje Mihanović <duje@dujemihanovic.xyz>









 */



















#ifndef __DTS_MARVELL_PXA1908_POWER_H









#define __DTS_MARVELL_PXA1908_POWER_H



















#define PXA1908_POWER_DOMAIN_VPU	0









#define PXA1908_POWER_DOMAIN_GPU	1









#define PXA1908_POWER_DOMAIN_GPU2D	2









#define PXA1908_POWER_DOMAIN_DSI	3









#define PXA1908_POWER_DOMAIN_ISP	4



















#endif