Commit 6143374c authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools arch x86: Sync the msr-index.h copy with the kernel sources 

To pick up the changes from these csets:

  159013a7 ("x86/its: Enumerate Indirect Target Selection (ITS) bug")
  f4138de5 ("x86/msr: Standardize on u64 in <asm/msr-index.h>")
  ec980e4f ("perf/x86/intel: Support auto counter reload")

That cause no changes to tooling as it doesn't include a new MSR to be
captured by the tools/perf/trace/beauty/tracepoints/x86_msr.sh script.

Just silences this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/aEtAUg83OQGx8Kay@x1


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 3417404c

tools/arch/x86/include/asm/msr-index.h

+10 −6
Original line number Diff line number Diff line
@@ -553,13 +553,13 @@ 
#define HWP_MIN_PERF(x)			(x & 0xff)

#define HWP_MAX_PERF(x)			((x & 0xff) << 8)

#define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)

#define HWP_ENERGY_PERF_PREFERENCE(x)	(((unsigned long long) x & 0xff) << 24)

#define HWP_ENERGY_PERF_PREFERENCE(x)	(((u64)x & 0xff) << 24)

#define HWP_EPP_PERFORMANCE		0x00

#define HWP_EPP_BALANCE_PERFORMANCE	0x80

#define HWP_EPP_BALANCE_POWERSAVE	0xC0

#define HWP_EPP_POWERSAVE		0xFF

#define HWP_ACTIVITY_WINDOW(x)		((unsigned long long)(x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((unsigned long long)(x & 0x1) << 42)

#define HWP_ACTIVITY_WINDOW(x)		((u64)(x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((u64)(x & 0x1) << 42)



/* IA32_HWP_STATUS */

#define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)
@@ -602,7 +602,11 @@ 
/* V6 PMON MSR range */

#define MSR_IA32_PMC_V6_GP0_CTR		0x1900

#define MSR_IA32_PMC_V6_GP0_CFG_A	0x1901

#define MSR_IA32_PMC_V6_GP0_CFG_B	0x1902

#define MSR_IA32_PMC_V6_GP0_CFG_C	0x1903

#define MSR_IA32_PMC_V6_FX0_CTR		0x1980

#define MSR_IA32_PMC_V6_FX0_CFG_B	0x1982

#define MSR_IA32_PMC_V6_FX0_CFG_C	0x1983

#define MSR_IA32_PMC_V6_STEP		4



/* KeyID partitioning between MKTME and TDX */