Commit 614351f4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2023-10-12' of... 

Merge tag 'drm-intel-gt-next-2023-10-12' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Driver Changes:

Fixes/improvements/new stuff:

- Register engines early to avoid type confusion (Mathias Krause)
- Suppress 'ignoring reset notification' message [guc] (John Harrison)
- Update 'recommended' version to 70.12.1 for DG2/ADL-S/ADL-P/MTL [guc] (John Harrison)
- Enable WA 14018913170 [guc, dg2] (Daniele Ceraolo Spurio)

Future platform enablement:

- Clean steer semaphore on resume (Nirmoy Das)
- Skip MCR ops for ring fault register [mtl] (Nirmoy Das)
- Make i915_gem_shrinker multi-gt aware [gem] (Jonathan Cavitt)
- Enable GGTT updates with binder in MTL (Nirmoy Das, Chris Wilson)
- Invalidate the TLBs on each GT (Chris Wilson)

Miscellaneous:

- Clarify type evolution of uabi_node/uabi_engines (Mathias Krause)
- Annotate struct ct_incoming_msg with __counted_by [guc] (Kees Cook)
- More use of GT specific print helpers [gt] (John Harrison)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZSfKotZVdypU6NaX@tursulin-desk
parents 7971debd 039adf39

drivers/gpu/drm/i915/gem/i915_gem_pages.c

+1 −1
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ static void flush_tlb_invalidate(struct drm_i915_gem_object *obj) 


	for_each_gt(gt, i915, id) {

		if (!obj->mm.tlb[id])

			return;

			continue;



		intel_gt_invalidate_tlb_full(gt, obj->mm.tlb[id]);

		obj->mm.tlb[id] = 0;

drivers/gpu/drm/i915/gem/i915_gem_shrinker.c

+26 −18
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/vmalloc.h>



#include "gt/intel_gt_requests.h"

#include "gt/intel_gt.h"



#include "i915_trace.h"
@@ -119,7 +120,8 @@ i915_gem_shrink(struct i915_gem_ww_ctx *ww, 
	intel_wakeref_t wakeref = 0;

	unsigned long count = 0;

	unsigned long scanned = 0;

	int err = 0;

	int err = 0, i = 0;

	struct intel_gt *gt;



	/* CHV + VTD workaround use stop_machine(); need to trylock vm->mutex */

	bool trylock_vm = !ww && intel_vm_no_concurrent_access_wa(i915);
@@ -147,9 +149,11 @@ i915_gem_shrink(struct i915_gem_ww_ctx *ww, 
	 * what we can do is give them a kick so that we do not keep idle

	 * contexts around longer than is necessary.

	 */

	if (shrink & I915_SHRINK_ACTIVE)

	if (shrink & I915_SHRINK_ACTIVE) {

		for_each_gt(gt, i915, i)

			/* Retire requests to unpin all idle contexts */

		intel_gt_retire_requests(to_gt(i915));

			intel_gt_retire_requests(gt);

	}



	/*

	 * As we may completely rewrite the (un)bound list whilst unbinding
@@ -389,6 +393,8 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr 
	struct i915_vma *vma, *next;

	unsigned long freed_pages = 0;

	intel_wakeref_t wakeref;

	struct intel_gt *gt;

	int i;



	with_intel_runtime_pm(&i915->runtime_pm, wakeref)

		freed_pages += i915_gem_shrink(NULL, i915, -1UL, NULL,
@@ -397,9 +403,10 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr 
					       I915_SHRINK_VMAPS);



	/* We also want to clear any cached iomaps as they wrap vmap */

	mutex_lock(&to_gt(i915)->ggtt->vm.mutex);

	for_each_gt(gt, i915, i) {

		mutex_lock(&gt->ggtt->vm.mutex);

		list_for_each_entry_safe(vma, next,

				 &to_gt(i915)->ggtt->vm.bound_list, vm_link) {

					 &gt->ggtt->vm.bound_list, vm_link) {

			unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;

			struct drm_i915_gem_object *obj = vma->obj;
@@ -414,7 +421,8 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr 


			i915_gem_object_unlock(obj);

		}

	mutex_unlock(&to_gt(i915)->ggtt->vm.mutex);

		mutex_unlock(&gt->ggtt->vm.mutex);

	}



	*(unsigned long *)ptr += freed_pages;

	return NOTIFY_DONE;

drivers/gpu/drm/i915/gt/intel_engine.h

+2 −0
Original line number Diff line number Diff line
@@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) 
#define I915_GEM_HWS_SEQNO		0x40

#define I915_GEM_HWS_SEQNO_ADDR		(I915_GEM_HWS_SEQNO * sizeof(u32))

#define I915_GEM_HWS_MIGRATE		(0x42 * sizeof(u32))

#define I915_GEM_HWS_GGTT_BIND		0x46

#define I915_GEM_HWS_GGTT_BIND_ADDR	(I915_GEM_HWS_GGTT_BIND * sizeof(u32))

#define I915_GEM_HWS_PXP		0x60

#define I915_GEM_HWS_PXP_ADDR		(I915_GEM_HWS_PXP * sizeof(u32))

#define I915_GEM_HWS_GSC		0x62

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+49 −20
Original line number Diff line number Diff line
@@ -316,8 +316,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 
			 * out in the wash.

			 */

			cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;

			drm_dbg(&gt->i915->drm,

				"graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",

			gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",

			       GRAPHICS_VER(gt->i915), cxt_size * 64,

			       cxt_size - 1);

			return round_up(cxt_size * 64, PAGE_SIZE);
@@ -788,7 +787,7 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) 


		if (!(BIT(i) & vdbox_mask)) {

			gt->info.engine_mask &= ~BIT(_VCS(i));

			drm_dbg(&i915->drm, "vcs%u fused off\n", i);

			gt_dbg(gt, "vcs%u fused off\n", i);

			continue;

		}
@@ -796,8 +795,7 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) 
			gt->info.vdbox_sfc_access |= BIT(i);

		logical_vdbox++;

	}

	drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",

		vdbox_mask, VDBOX_MASK(gt));

	gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));

	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));



	for (i = 0; i < I915_MAX_VECS; i++) {
@@ -808,11 +806,10 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) 


		if (!(BIT(i) & vebox_mask)) {

			gt->info.engine_mask &= ~BIT(_VECS(i));

			drm_dbg(&i915->drm, "vecs%u fused off\n", i);

			gt_dbg(gt, "vecs%u fused off\n", i);

		}

	}

	drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",

		vebox_mask, VEBOX_MASK(gt));

	gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));

	GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));

}
@@ -838,7 +835,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) 
	 */

	for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {

		info->engine_mask &= ~BIT(_CCS(i));

		drm_dbg(&i915->drm, "ccs%u fused off\n", i);

		gt_dbg(gt, "ccs%u fused off\n", i);

	}

}
@@ -866,8 +863,8 @@ static void engine_mask_apply_copy_fuses(struct intel_gt *gt) 
						   _BCS(instance));



		if (mask & info->engine_mask) {

			drm_dbg(&i915->drm, "bcs%u fused off\n", instance);

			drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);

			gt_dbg(gt, "bcs%u fused off\n", instance);

			gt_dbg(gt, "bcs%u fused off\n", instance + 1);



			info->engine_mask &= ~mask;

		}
@@ -907,8 +904,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 
	 *    submission, which will wake up the GSC power well.

	 */

	if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(&gt->uc)) {

		drm_notice(&gt->i915->drm,

			   "No GSC FW selected, disabling GSC CS and media C6\n");

		gt_notice(gt, "No GSC FW selected, disabling GSC CS and media C6\n");

		info->engine_mask &= ~BIT(GSC0);

	}
@@ -1097,8 +1093,7 @@ static int init_status_page(struct intel_engine_cs *engine) 
	 */

	obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);

	if (IS_ERR(obj)) {

		drm_err(&engine->i915->drm,

			"Failed to allocate status page\n");

		gt_err(engine->gt, "Failed to allocate status page\n");

		return PTR_ERR(obj);

	}
@@ -1418,6 +1413,20 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce) 
	intel_context_put(ce);

}



static struct intel_context *

create_ggtt_bind_context(struct intel_engine_cs *engine)

{

	static struct lock_class_key kernel;



	/*

	 * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple

	 * bind requets at a time so get a bigger ring.

	 */

	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,

						  I915_GEM_HWS_GGTT_BIND_ADDR,

						  &kernel, "ggtt_bind_context");

}



static struct intel_context *

create_kernel_context(struct intel_engine_cs *engine)

{
@@ -1441,7 +1450,7 @@ create_kernel_context(struct intel_engine_cs *engine) 
 */

static int engine_init_common(struct intel_engine_cs *engine)

{

	struct intel_context *ce;

	struct intel_context *ce, *bce = NULL;

	int ret;



	engine->set_default_submission(engine);
@@ -1457,17 +1466,33 @@ static int engine_init_common(struct intel_engine_cs *engine) 
	ce = create_kernel_context(engine);

	if (IS_ERR(ce))

		return PTR_ERR(ce);

	/*

	 * Create a separate pinned context for GGTT update with blitter engine

	 * if a platform require such service. MI_UPDATE_GTT works on other

	 * engines as well but BCS should be less busy engine so pick that for

	 * GGTT updates.

	 */

	if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {

		bce = create_ggtt_bind_context(engine);

		if (IS_ERR(bce)) {

			ret = PTR_ERR(bce);

			goto err_ce_context;

		}

	}



	ret = measure_breadcrumb_dw(ce);

	if (ret < 0)

		goto err_context;

		goto err_bce_context;



	engine->emit_fini_breadcrumb_dw = ret;

	engine->kernel_context = ce;

	engine->bind_context = bce;



	return 0;



err_context:

err_bce_context:

	intel_engine_destroy_pinned_context(bce);

err_ce_context:

	intel_engine_destroy_pinned_context(ce);

	return ret;

}
@@ -1537,6 +1562,10 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) 
	if (engine->kernel_context)

		intel_engine_destroy_pinned_context(engine->kernel_context);



	if (engine->bind_context)

		intel_engine_destroy_pinned_context(engine->bind_context);





	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));

	cleanup_status_page(engine);

drivers/gpu/drm/i915/gt/intel_engine_types.h

+12 −1
Original line number Diff line number Diff line
@@ -402,7 +402,15 @@ struct intel_engine_cs { 


	unsigned long context_tag;



	/*

	 * The type evolves during initialization, see related comment for

	 * struct drm_i915_private's uabi_engines member.

	 */

	union {

		struct llist_node uabi_llist;

		struct list_head uabi_list;

		struct rb_node uabi_node;

	};



	struct intel_sseu sseu;
@@ -416,6 +424,9 @@ struct intel_engine_cs { 
	struct llist_head barrier_tasks;



	struct intel_context *kernel_context; /* pinned */

	struct intel_context *bind_context; /* pinned, only for BCS0 */

	/* mark the bind context's availability status */

	bool bind_context_ready;



	/**

	 * pinned_contexts_list: List of pinned contexts. This list is only