Commit 6156424a authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-v6.19-1' of... 

Merge tag 'intel-pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel

 into devel

intel-pinctrl for v6.19-1

* Add and use common macro INTEL_GPP() to avoid duplication
* Export intel_gpio_add_pin_ranges() and reuse it instead of custom copies
* Unify error messages with help of dev_err_probe()

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents ebd61482 8daf70e6

drivers/pinctrl/intel/pinctrl-alderlake.c

+30 −38
Original line number Diff line number Diff line
@@ -27,14 +27,6 @@ 
#define ADL_S_GPI_IS		0x200

#define ADL_S_GPI_IE		0x220



#define ADL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



#define ADL_N_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
@@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = { 
};



static const struct intel_padgroup adln_community0_gpps[] = {

	ADL_GPP(0, 0, 25, 0),				/* GPP_B */

	ADL_GPP(1, 26, 41, 32),				/* GPP_T */

	ADL_GPP(2, 42, 66, 64),				/* GPP_A */

	INTEL_GPP(0, 0, 25, 0),				/* GPP_B */

	INTEL_GPP(1, 26, 41, 32),			/* GPP_T */

	INTEL_GPP(2, 42, 66, 64),			/* GPP_A */

};



static const struct intel_padgroup adln_community1_gpps[] = {

	ADL_GPP(0, 67, 74, 96),				/* GPP_S */

	ADL_GPP(1, 75, 94, 128),			/* GPP_I */

	ADL_GPP(2, 95, 118, 160),			/* GPP_H */

	ADL_GPP(3, 119, 139, 192),			/* GPP_D */

	ADL_GPP(4, 140, 168, 224),			/* vGPIO */

	INTEL_GPP(0, 67, 74, 96),			/* GPP_S */

	INTEL_GPP(1, 75, 94, 128),			/* GPP_I */

	INTEL_GPP(2, 95, 118, 160),			/* GPP_H */

	INTEL_GPP(3, 119, 139, 192),			/* GPP_D */

	INTEL_GPP(4, 140, 168, 224),			/* vGPIO */

};



static const struct intel_padgroup adln_community4_gpps[] = {

	ADL_GPP(0, 169, 192, 256),			/* GPP_C */

	ADL_GPP(1, 193, 217, 288),			/* GPP_F */

	ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	ADL_GPP(3, 224, 248, 320),			/* GPP_E */

	INTEL_GPP(0, 169, 192, 256),			/* GPP_C */

	INTEL_GPP(1, 193, 217, 288),			/* GPP_F */

	INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(3, 224, 248, 320),			/* GPP_E */

};



static const struct intel_padgroup adln_community5_gpps[] = {

	ADL_GPP(0, 249, 256, 352),			/* GPP_R */

	INTEL_GPP(0, 249, 256, 352),			/* GPP_R */

};



static const struct intel_community adln_communities[] = {
@@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = { 
};



static const struct intel_padgroup adls_community0_gpps[] = {

	ADL_GPP(0, 0, 24, 0),				/* GPP_I */

	ADL_GPP(1, 25, 47, 32),				/* GPP_R */

	ADL_GPP(2, 48, 59, 64),				/* GPP_J */

	ADL_GPP(3, 60, 86, 96),				/* vGPIO */

	ADL_GPP(4, 87, 94, 128),			/* vGPIO_0 */

	INTEL_GPP(0, 0, 24, 0),				/* GPP_I */

	INTEL_GPP(1, 25, 47, 32),			/* GPP_R */

	INTEL_GPP(2, 48, 59, 64),			/* GPP_J */

	INTEL_GPP(3, 60, 86, 96),			/* vGPIO */

	INTEL_GPP(4, 87, 94, 128),			/* vGPIO_0 */

};



static const struct intel_padgroup adls_community1_gpps[] = {

	ADL_GPP(0, 95, 118, 160),			/* GPP_B */

	ADL_GPP(1, 119, 126, 192),			/* GPP_G */

	ADL_GPP(2, 127, 150, 224),			/* GPP_H */

	INTEL_GPP(0, 95, 118, 160),			/* GPP_B */

	INTEL_GPP(1, 119, 126, 192),			/* GPP_G */

	INTEL_GPP(2, 127, 150, 224),			/* GPP_H */

};



static const struct intel_padgroup adls_community3_gpps[] = {

	ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP),	/* SPI0 */

	ADL_GPP(1, 160, 175, 256),			/* GPP_A */

	ADL_GPP(2, 176, 199, 288),			/* GPP_C */

	INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP),	/* SPI0 */

	INTEL_GPP(1, 160, 175, 256),			/* GPP_A */

	INTEL_GPP(2, 176, 199, 288),			/* GPP_C */

};



static const struct intel_padgroup adls_community4_gpps[] = {

	ADL_GPP(0, 200, 207, 320),			/* GPP_S */

	ADL_GPP(1, 208, 230, 352),			/* GPP_E */

	ADL_GPP(2, 231, 245, 384),			/* GPP_K */

	ADL_GPP(3, 246, 269, 416),			/* GPP_F */

	INTEL_GPP(0, 200, 207, 320),			/* GPP_S */

	INTEL_GPP(1, 208, 230, 352),			/* GPP_E */

	INTEL_GPP(2, 231, 245, 384),			/* GPP_K */

	INTEL_GPP(3, 246, 269, 416),			/* GPP_F */

};



static const struct intel_padgroup adls_community5_gpps[] = {

	ADL_GPP(0, 270, 294, 448),			/* GPP_D */

	ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(0, 270, 294, 448),			/* GPP_D */

	INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

};



static const struct intel_community adls_communities[] = {

drivers/pinctrl/intel/pinctrl-baytrail.c

+8 −12
Original line number Diff line number Diff line
@@ -1498,9 +1498,9 @@ static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) 


	ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);

	if (ret)

		dev_err(dev, "failed to add GPIO pin range\n");

		return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");



	return ret;

	return 0;

}



static int byt_gpio_probe(struct intel_pinctrl *vg)
@@ -1548,9 +1548,9 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) 


	ret = devm_gpiochip_add_data(vg->dev, gc, vg);

	if (ret)

		dev_err(vg->dev, "failed adding byt-gpio chip\n");

		return dev_err_probe(vg->dev, ret, "failed to register gpiochip\n");



	return ret;

	return 0;

}



static int byt_set_soc_data(struct intel_pinctrl *vg,
@@ -1601,10 +1601,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev) 


	vg->dev = dev;

	ret = byt_set_soc_data(vg, soc_data);

	if (ret) {

		dev_err(dev, "failed to set soc data\n");

		return ret;

	}

	if (ret)

		return dev_err_probe(dev, ret, "failed to set soc data\n");



	vg->pctldesc		= byt_pinctrl_desc;

	vg->pctldesc.name	= dev_name(dev);
@@ -1612,10 +1610,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev) 
	vg->pctldesc.npins	= vg->soc->npins;



	vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);

	if (IS_ERR(vg->pctldev)) {

		dev_err(dev, "failed to register pinctrl driver\n");

		return PTR_ERR(vg->pctldev);

	}

	if (IS_ERR(vg->pctldev))

		return dev_err_probe(dev, PTR_ERR(vg->pctldev), "failed to register pinctrl\n");



	ret = byt_gpio_probe(vg);

	if (ret)

drivers/pinctrl/intel/pinctrl-cannonlake.c

+30 −38
Original line number Diff line number Diff line
@@ -28,14 +28,6 @@ 
#define CNL_H_GPI_IS		0x100

#define CNL_H_GPI_IE		0x120



#define CNL_GPP(r, s, e, g)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

		.gpio_base = (g),			\

	}



#define CNL_LP_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = { 
};



static const struct intel_padgroup cnlh_community0_gpps[] = {

	CNL_GPP(0, 0, 24, 0),			/* GPP_A */

	CNL_GPP(1, 25, 50, 32),			/* GPP_B */

	INTEL_GPP(0, 0, 24, 0),				/* GPP_A */

	INTEL_GPP(1, 25, 50, 32),			/* GPP_B */

};



static const struct intel_padgroup cnlh_community1_gpps[] = {

	CNL_GPP(0, 51, 74, 64),				/* GPP_C */

	CNL_GPP(1, 75, 98, 96),				/* GPP_D */

	CNL_GPP(2, 99, 106, 128),			/* GPP_G */

	CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP),	/* AZA */

	CNL_GPP(4, 115, 146, 160),			/* vGPIO_0 */

	CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP),	/* vGPIO_1 */

	INTEL_GPP(0, 51, 74, 64),			/* GPP_C */

	INTEL_GPP(1, 75, 98, 96),			/* GPP_D */

	INTEL_GPP(2, 99, 106, 128),			/* GPP_G */

	INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP),	/* AZA */

	INTEL_GPP(4, 115, 146, 160),			/* vGPIO_0 */

	INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP),	/* vGPIO_1 */

};



static const struct intel_padgroup cnlh_community3_gpps[] = {

	CNL_GPP(0, 155, 178, 192),			/* GPP_K */

	CNL_GPP(1, 179, 202, 224),			/* GPP_H */

	CNL_GPP(2, 203, 215, 256),			/* GPP_E */

	CNL_GPP(3, 216, 239, 288),			/* GPP_F */

	CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(0, 155, 178, 192),			/* GPP_K */

	INTEL_GPP(1, 179, 202, 224),			/* GPP_H */

	INTEL_GPP(2, 203, 215, 256),			/* GPP_E */

	INTEL_GPP(3, 216, 239, 288),			/* GPP_F */

	INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP),	/* SPI */

};



static const struct intel_padgroup cnlh_community4_gpps[] = {

	CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP),	/* CPU */

	CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	CNL_GPP(2, 269, 286, 320),			/* GPP_I */

	CNL_GPP(3, 287, 298, 352),			/* GPP_J */

	INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP),	/* CPU */

	INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(2, 269, 286, 320),			/* GPP_I */

	INTEL_GPP(3, 287, 298, 352),			/* GPP_J */

};



static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = { 
};



static const struct intel_padgroup cnllp_community0_gpps[] = {

	CNL_GPP(0, 0, 24, 0),				/* GPP_A */

	CNL_GPP(1, 25, 50, 32),				/* GPP_B */

	CNL_GPP(2, 51, 58, 64),				/* GPP_G */

	CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP),	/* SPI */

	INTEL_GPP(0, 0, 24, 0),				/* GPP_A */

	INTEL_GPP(1, 25, 50, 32),			/* GPP_B */

	INTEL_GPP(2, 51, 58, 64),			/* GPP_G */

	INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP),	/* SPI */

};



static const struct intel_padgroup cnllp_community1_gpps[] = {

	CNL_GPP(0, 68, 92, 96),				/* GPP_D */

	CNL_GPP(1, 93, 116, 128),			/* GPP_F */

	CNL_GPP(2, 117, 140, 160),			/* GPP_H */

	CNL_GPP(3, 141, 172, 192),			/* vGPIO */

	CNL_GPP(4, 173, 180, 224),			/* vGPIO */

	INTEL_GPP(0, 68, 92, 96),			/* GPP_D */

	INTEL_GPP(1, 93, 116, 128),			/* GPP_F */

	INTEL_GPP(2, 117, 140, 160),			/* GPP_H */

	INTEL_GPP(3, 141, 172, 192),			/* vGPIO */

	INTEL_GPP(4, 173, 180, 224),			/* vGPIO */

};



static const struct intel_padgroup cnllp_community4_gpps[] = {

	CNL_GPP(0, 181, 204, 256),			/* GPP_C */

	CNL_GPP(1, 205, 228, 288),			/* GPP_E */

	CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

	INTEL_GPP(0, 181, 204, 256),			/* GPP_C */

	INTEL_GPP(1, 205, 228, 288),			/* GPP_E */

	INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP),	/* JTAG */

	INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */

};



static const struct intel_community cnllp_communities[] = {

drivers/pinctrl/intel/pinctrl-cedarfork.c

+15 −22
Original line number Diff line number Diff line
@@ -21,13 +21,6 @@ 
#define CDF_GPI_IS	0x200

#define CDF_GPI_IE	0x230



#define CDF_GPP(r, s, e)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

	}



#define CDF_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
@@ -288,24 +281,24 @@ static const struct pinctrl_pin_desc cdf_pins[] = { 
};



static const struct intel_padgroup cdf_community0_gpps[] = {

	CDF_GPP(0, 0, 23),	/* WEST2 */

	CDF_GPP(1, 24, 47),	/* WEST3 */

	CDF_GPP(2, 48, 70),	/* WEST01 */

	CDF_GPP(3, 71, 90),	/* WEST5 */

	CDF_GPP(4, 91, 96),	/* WESTC */

	CDF_GPP(5, 97, 101),	/* WESTC_DFX */

	CDF_GPP(6, 102, 111),	/* WESTA */

	CDF_GPP(7, 112, 123),	/* WESTB */

	CDF_GPP(8, 124, 143),	/* WESTD */

	CDF_GPP(9, 144, 144),	/* WESTD_PECI */

	CDF_GPP(10, 145, 167),	/* WESTF */

	INTEL_GPP(0, 0, 23, 0),		/* WEST2 */

	INTEL_GPP(1, 24, 47, 24),	/* WEST3 */

	INTEL_GPP(2, 48, 70, 48),	/* WEST01 */

	INTEL_GPP(3, 71, 90, 71),	/* WEST5 */

	INTEL_GPP(4, 91, 96, 91),	/* WESTC */

	INTEL_GPP(5, 97, 101, 97),	/* WESTC_DFX */

	INTEL_GPP(6, 102, 111, 102),	/* WESTA */

	INTEL_GPP(7, 112, 123, 112),	/* WESTB */

	INTEL_GPP(8, 124, 143, 124),	/* WESTD */

	INTEL_GPP(9, 144, 144, 144),	/* WESTD_PECI */

	INTEL_GPP(10, 145, 167, 145),	/* WESTF */

};



static const struct intel_padgroup cdf_community1_gpps[] = {

	CDF_GPP(0, 168, 191),	/* EAST2 */

	CDF_GPP(1, 192, 202),	/* EAST3 */

	CDF_GPP(2, 203, 225),	/* EAST0 */

	CDF_GPP(3, 226, 236),	/* EMMC */

	INTEL_GPP(0, 168, 191, 168),	/* EAST2 */

	INTEL_GPP(1, 192, 202, 192),	/* EAST3 */

	INTEL_GPP(2, 203, 225, 203),	/* EAST0 */

	INTEL_GPP(3, 226, 236, 226),	/* EMMC */

};



static const struct intel_community cdf_communities[] = {

drivers/pinctrl/intel/pinctrl-cherryview.c

+27 −59
Original line number Diff line number Diff line
@@ -92,12 +92,6 @@ struct intel_community_context { 


#define PINMODE(m, i)		((m) | ((i) * PINMODE_INVERT_OE))



#define CHV_GPP(start, end)			\

	{					\

		.base = (start),		\

		.size = (end) - (start) + 1,	\

	}



#define CHV_COMMUNITY(g, i, a)			\

	{					\

		.gpps = (g),			\
@@ -258,13 +252,13 @@ static const struct intel_function southwest_functions[] = { 
};



static const struct intel_padgroup southwest_gpps[] = {

	CHV_GPP(0, 7),

	CHV_GPP(15, 22),

	CHV_GPP(30, 37),

	CHV_GPP(45, 52),

	CHV_GPP(60, 67),

	CHV_GPP(75, 82),

	CHV_GPP(90, 97),

	INTEL_GPP(0, 0, 7, 0),

	INTEL_GPP(1, 15, 22, 15),

	INTEL_GPP(2, 30, 37, 30),

	INTEL_GPP(3, 45, 52, 45),

	INTEL_GPP(4, 60, 67, 60),

	INTEL_GPP(5, 75, 82, 75),

	INTEL_GPP(6, 90, 97, 90),

};



/*
@@ -354,11 +348,11 @@ static const struct pinctrl_pin_desc north_pins[] = { 
};



static const struct intel_padgroup north_gpps[] = {

	CHV_GPP(0, 8),

	CHV_GPP(15, 27),

	CHV_GPP(30, 41),

	CHV_GPP(45, 56),

	CHV_GPP(60, 72),

	INTEL_GPP(0, 0, 8, 0),

	INTEL_GPP(1, 15, 27, 15),

	INTEL_GPP(2, 30, 41, 30),

	INTEL_GPP(3, 45, 56, 45),

	INTEL_GPP(4, 60, 72, 60),

};



/*
@@ -406,8 +400,8 @@ static const struct pinctrl_pin_desc east_pins[] = { 
};



static const struct intel_padgroup east_gpps[] = {

	CHV_GPP(0, 11),

	CHV_GPP(15, 26),

	INTEL_GPP(0, 0, 11, 0),

	INTEL_GPP(1, 15, 26, 15),

};



static const struct intel_community east_communities[] = {
@@ -526,12 +520,12 @@ static const struct intel_function southeast_functions[] = { 
};



static const struct intel_padgroup southeast_gpps[] = {

	CHV_GPP(0, 7),

	CHV_GPP(15, 26),

	CHV_GPP(30, 35),

	CHV_GPP(45, 52),

	CHV_GPP(60, 69),

	CHV_GPP(75, 85),

	INTEL_GPP(0, 0, 7, 0),

	INTEL_GPP(1, 15, 26, 15),

	INTEL_GPP(2, 30, 35, 30),

	INTEL_GPP(3, 45, 52, 45),

	INTEL_GPP(4, 60, 69, 60),

	INTEL_GPP(5, 75, 85, 75),

};



static const struct intel_community southeast_communities[] = {
@@ -1517,26 +1511,6 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip) 
	return 0;

}



static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)

{

	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);

	struct device *dev = pctrl->dev;

	const struct intel_community *community = &pctrl->communities[0];

	const struct intel_padgroup *gpp;

	int ret, i;



	for (i = 0; i < community->ngpps; i++) {

		gpp = &community->gpps[i];

		ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);

		if (ret) {

			dev_err(dev, "failed to add GPIO pin range\n");

			return ret;

		}

	}



	return 0;

}



static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)

{

	const struct intel_community *community = &pctrl->communities[0];
@@ -1550,7 +1524,7 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 


	chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;

	chip->label = dev_name(dev);

	chip->add_pin_ranges = chv_gpio_add_pin_ranges;

	chip->add_pin_ranges = intel_gpio_add_pin_ranges;

	chip->parent = dev;

	chip->base = -1;
@@ -1567,17 +1541,13 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 
		chip->irq.init_valid_mask = chv_init_irq_valid_mask;

	} else {

		irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);

		if (irq_base < 0) {

			dev_err(dev, "Failed to allocate IRQ numbers\n");

			return irq_base;

		}

		if (irq_base < 0)

			return dev_err_probe(dev, irq_base, "failed to allocate IRQ numbers\n");

	}



	ret = devm_gpiochip_add_data(dev, chip, pctrl);

	if (ret) {

		dev_err(dev, "Failed to register gpiochip\n");

		return ret;

	}

	if (ret)

		return dev_err_probe(dev, ret, "failed to register gpiochip\n");



	if (!need_valid_mask) {

		for (i = 0; i < community->ngpps; i++) {
@@ -1673,10 +1643,8 @@ static int chv_pinctrl_probe(struct platform_device *pdev) 
	pctrl->pctldesc.npins = pctrl->soc->npins;



	pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);

	if (IS_ERR(pctrl->pctldev)) {

		dev_err(dev, "failed to register pinctrl driver\n");

		return PTR_ERR(pctrl->pctldev);

	}

	if (IS_ERR(pctrl->pctldev))

		return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n");



	ret = chv_gpio_probe(pctrl, irq);

	if (ret)