Commit 6186199f authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Use emit_clock_levels in vega20



Move to emit_clock_levels from print_clock_levels

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0229122f
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+132 −79
Original line number Diff line number Diff line
@@ -3362,8 +3362,9 @@ static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
	return link_speed[speed_level];
}

static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
		enum pp_clock_type type, char *buf)
static int vega20_emit_clock_levels(struct pp_hwmgr *hwmgr,
				    enum pp_clock_type type, char *buf,
				    int *offset)
{
	struct vega20_hwmgr *data =
			(struct vega20_hwmgr *)(hwmgr->backend);
@@ -3375,7 +3376,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
	struct pp_clock_levels_with_latency clocks;
	struct vega20_single_dpm_table *fclk_dpm_table =
			&(data->dpm_table.fclk_table);
	int i, now, size = 0;
	int i, now, size = *offset;
	int ret = 0;
	uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;

@@ -3387,15 +3388,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
				return ret);

		if (vega20_get_sclks(hwmgr, &clocks)) {
			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
			size += sysfs_emit_at(buf, size,
					      "0: %uMhz * (DPM disabled)\n",
					      now / 100);
			break;
		}

		for (i = 0; i < clocks.num_levels; i++)
			size += sprintf(buf + size, "%d: %uMhz %s\n",
				i, clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
			size += sysfs_emit_at(
				buf, size, "%d: %uMhz %s\n", i,
				clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ?
					"*" :
					"");
		break;

	case PP_MCLK:
@@ -3405,15 +3410,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
				return ret);

		if (vega20_get_memclocks(hwmgr, &clocks)) {
			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
			size += sysfs_emit_at(buf, size,
					      "0: %uMhz * (DPM disabled)\n",
					      now / 100);
			break;
		}

		for (i = 0; i < clocks.num_levels; i++)
			size += sprintf(buf + size, "%d: %uMhz %s\n",
				i, clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
			size += sysfs_emit_at(
				buf, size, "%d: %uMhz %s\n", i,
				clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ?
					"*" :
					"");
		break;

	case PP_SOCCLK:
@@ -3423,15 +3432,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
				return ret);

		if (vega20_get_socclocks(hwmgr, &clocks)) {
			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
			size += sysfs_emit_at(buf, size,
					      "0: %uMhz * (DPM disabled)\n",
					      now / 100);
			break;
		}

		for (i = 0; i < clocks.num_levels; i++)
			size += sprintf(buf + size, "%d: %uMhz %s\n",
				i, clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
			size += sysfs_emit_at(
				buf, size, "%d: %uMhz %s\n", i,
				clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ?
					"*" :
					"");
		break;

	case PP_FCLK:
@@ -3441,9 +3454,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
				return ret);

		for (i = 0; i < fclk_dpm_table->count; i++)
			size += sprintf(buf + size, "%d: %uMhz %s\n",
				i, fclk_dpm_table->dpm_levels[i].value,
				fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
			size += sysfs_emit_at(
				buf, size, "%d: %uMhz %s\n", i,
				fclk_dpm_table->dpm_levels[i].value,
				fclk_dpm_table->dpm_levels[i].value ==
						(now / 100) ?
					"*" :
					"");
		break;

	case PP_DCEFCLK:
@@ -3453,15 +3470,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
				return ret);

		if (vega20_get_dcefclocks(hwmgr, &clocks)) {
			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
			size += sysfs_emit_at(buf, size,
					      "0: %uMhz * (DPM disabled)\n",
					      now / 100);
			break;
		}

		for (i = 0; i < clocks.num_levels; i++)
			size += sprintf(buf + size, "%d: %uMhz %s\n",
				i, clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
			size += sysfs_emit_at(
				buf, size, "%d: %uMhz %s\n", i,
				clocks.data[i].clocks_in_khz / 1000,
				(clocks.data[i].clocks_in_khz == now * 10) ?
					"*" :
					"");
		break;

	case PP_PCIE:
@@ -3473,39 +3494,44 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
			gen_speed = pptable->PcieGenSpeed[i];
			lane_width = pptable->PcieLaneCount[i];

			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
			size += sysfs_emit_at(
				buf, size, "%d: %s %s %dMhz %s\n", i,
				(gen_speed == 0) ? "2.5GT/s," :
				(gen_speed == 1) ? "5.0GT/s," :
				(gen_speed == 2) ? "8.0GT/s," :
					(gen_speed == 3) ? "16.0GT/s," : "",
				(gen_speed == 3) ? "16.0GT/s," :
						   "",
				(lane_width == 1) ? "x1" :
				(lane_width == 2) ? "x2" :
				(lane_width == 3) ? "x4" :
				(lane_width == 4) ? "x8" :
				(lane_width == 5) ? "x12" :
					(lane_width == 6) ? "x16" : "",
				(lane_width == 6) ? "x16" :
						    "",
				pptable->LclkFreq[i],
				(current_gen_speed == gen_speed) &&
					(current_lane_width == lane_width) ?
					"*" : "");
						(current_lane_width ==
						 lane_width) ?
					"*" :
					"");
		}
		break;

	case OD_SCLK:
		if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
		    od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
			size += sprintf(buf + size, "%s:\n", "OD_SCLK");
			size += sprintf(buf + size, "0: %10uMhz\n",
			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
					      od_table->GfxclkFmin);
			size += sprintf(buf + size, "1: %10uMhz\n",
			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
					      od_table->GfxclkFmax);
		}
		break;

	case OD_MCLK:
		if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
			size += sprintf(buf + size, "%s:\n", "OD_MCLK");
			size += sprintf(buf + size, "1: %10uMhz\n",
			size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
					      od_table->UclkFmax);
		}

@@ -3518,32 +3544,38 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
			size += sprintf(buf + size, "%s:\n", "OD_VDDC_CURVE");
			size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
			size += sysfs_emit_at(buf, size, "%s:\n",
					      "OD_VDDC_CURVE");
			size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n",
					      od_table->GfxclkFreq1,
				od_table->GfxclkVolt1 / VOLTAGE_SCALE);
			size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
					      od_table->GfxclkVolt1 /
						      VOLTAGE_SCALE);
			size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n",
					      od_table->GfxclkFreq2,
				od_table->GfxclkVolt2 / VOLTAGE_SCALE);
			size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
					      od_table->GfxclkVolt2 /
						      VOLTAGE_SCALE);
			size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n",
					      od_table->GfxclkFreq3,
				od_table->GfxclkVolt3 / VOLTAGE_SCALE);
					      od_table->GfxclkVolt3 /
						      VOLTAGE_SCALE);
		}

		break;

	case OD_RANGE:
		size += sprintf(buf + size, "%s:\n", "OD_RANGE");
		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");

		if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
		    od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
			size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
			size += sysfs_emit_at(
				buf, size, "SCLK: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
				od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
		}

		if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
			size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
			size += sysfs_emit_at(
				buf, size, "MCLK: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
				od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
		}
@@ -3554,31 +3586,52 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
			size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
			size += sysfs_emit_at(
				buf, size,
				"VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
				od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
			size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
			size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_GFXCLK_FREQ1]
					.max_value);
			size += sysfs_emit_at(
				buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1]
					.min_value,
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1]
					.max_value);
			size += sysfs_emit_at(
				buf, size,
				"VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
				od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
			size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
			size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_GFXCLK_FREQ2]
					.max_value);
			size += sysfs_emit_at(
				buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2]
					.min_value,
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2]
					.max_value);
			size += sysfs_emit_at(
				buf, size,
				"VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
				od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
				od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
			size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
				od8_settings[OD8_SETTING_GFXCLK_FREQ3]
					.max_value);
			size += sysfs_emit_at(
				buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3]
					.min_value,
				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3]
					.max_value);
		}

		break;
	default:
		break;
	}
	return size;

	*offset = size;

	return 0;
}

static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
@@ -4412,7 +4465,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
	.odn_edit_dpm_table = vega20_odn_edit_dpm_table,
	/* for sysfs to retrive/set gfxclk/memclk */
	.force_clock_level = vega20_force_clock_level,
	.print_clock_levels = vega20_print_clock_levels,
	.emit_clock_levels = vega20_emit_clock_levels,
	.read_sensor = vega20_read_sensor,
	.get_ppfeature_status = vega20_get_ppfeature_status,
	.set_ppfeature_status = vega20_set_ppfeature_status,