Commit 61926c91 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-next-2025-11-05' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next 



UAPI Changes:

Limit number of jobs per exec queue (Shuicheng)
Add sriov_admin sysfs tree (Michal)

Driver Changes:

Fix an uninitialized value (Thomas)
Expose a residency counter through debugfs (Mohammed Thasleem)
Workaround enabling and improvement (Tapani, Tangudu)
More Crescent Island-specific support (Sk Anirban, Lucas)
PAT entry dump imprement (Xin)
Inline gt_reset in the worker (Lucas)
Synchronize GT reset with device unbind (Balasubramani)
Do clean shutdown also when using flr (Jouni)
Fix serialization on burst of unbinds (Matt Brost)
Pagefault Refactor (Matt Brost)
Remove some unused code (Gwan-gyeong)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
Link: https://patch.msgid.link/aQuBECxNOhudc0Bz@fedora
parents 2a084f4a 424e2cce

Documentation/ABI/testing/sysfs-driver-intel-xe-sriov

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+159 −0
Original line number Diff line number Diff line 
What:		/sys/bus/pci/drivers/xe/.../sriov_admin/

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		This directory appears for the particular Intel Xe device when:



		 - device supports SR-IOV, and

		 - device is a Physical Function (PF), and

		 - driver support for the SR-IOV PF is enabled on given device.



		This directory is used as a root for all attributes required to

		manage both Physical Function (PF) and Virtual Functions (VFs).





What:		/sys/bus/pci/drivers/xe/.../sriov_admin/pf/

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		This directory holds attributes related to the SR-IOV Physical

		Function (PF).





What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf1/

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf2/

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf<N>/

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		These directories hold attributes related to the SR-IOV Virtual

		Functions (VFs).



		Note that the VF number <N> is 1-based as described in PCI SR-IOV

		specification as the Xe driver follows that naming schema.



		There could be "vf1", "vf2" and so on, up to "vf<N>", where <N>

		matches the value of the "sriov_totalvfs" attribute.





What:		/sys/bus/pci/drivers/xe/.../sriov_admin/pf/profile/exec_quantum_ms

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/pf/profile/preempt_timeout_us

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/pf/profile/sched_priority

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf<n>/profile/exec_quantum_ms

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf<n>/profile/preempt_timeout_us

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf<n>/profile/sched_priority

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		These files expose scheduling parameters for the PF and its VFs, and

		are visible only on Intel Xe platforms that use time-sliced GPU sharing.

		They can be changed even if VFs are enabled and running and reflect the

		settings of all tiles/GTs assigned to the given function.



		exec_quantum_ms: (RW) unsigned integer

			The GT execution quantum (EQ) in [ms] for the given function.

			Actual quantum value might be aligned per HW/FW requirements.



			Default is 0 (unlimited).



		preempt_timeout_us: (RW) unsigned integer

			The GT preemption timeout in [us] of the given function.

			Actual timeout value might be aligned per HW/FW requirements.



			Default is 0 (unlimited).



		sched_priority: (RW/RO) string

			The GT scheduling priority of the given function.



			"low" - function will be scheduled on the GPU for its EQ/PT

				only if function has any work already submitted.



			"normal" - functions will be scheduled on the GPU for its EQ/PT

				irrespective of whether it has submitted a work or not.



			"high" - function will be scheduled on the GPU for its EQ/PT

				in the next time-slice after the current one completes

				and function has a work submitted.



			Default is "low".



			When read, this file will display the current and available

			scheduling priorities. The currently active priority level will

			be enclosed in square brackets, like:



				[low] normal high



			This file can be read-only if changing the priority is not

			supported.



		Writes to these attributes may fail with errors like:

			-EINVAL if provided input is malformed or not recognized,

			-EPERM if change is not applicable on given HW/FW,

			-EIO if FW refuses to change the provisioning.



		Reads from these attributes may fail with:

			-EUCLEAN if value is not consistent across all tiles/GTs.





What:		/sys/bus/pci/drivers/xe/.../sriov_admin/.bulk_profile/exec_quantum_ms

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/.bulk_profile/preempt_timeout_us

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/.bulk_profile/sched_priority

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		These files allows bulk reconfiguration of the scheduling parameters

		of the PF or VFs and are available only for Intel Xe platforms with

		GPU sharing based on the time-slice basis. These scheduling parameters

		can be changed even if VFs are enabled and running.



		exec_quantum_ms: (WO) unsigned integer

			The GT execution quantum (EQ) in [ms] to be applied to all functions.

			See sriov_admin/{pf,vf<N>}/profile/exec_quantum_ms for more details.



		preempt_timeout_us: (WO) unsigned integer

			The GT preemption timeout (PT) in [us] to be applied to all functions.

			See sriov_admin/{pf,vf<N>}/profile/preempt_timeout_us for more details.



		sched_priority: (RW/RO) string

			The GT scheduling priority to be applied for all functions.

			See sriov_admin/{pf,vf<N>}/profile/sched_priority for more details.



		Writes to these attributes may fail with errors like:

			-EINVAL if provided input is malformed or not recognized,

			-EPERM if change is not applicable on given HW/FW,

			-EIO if FW refuses to change the provisioning.





What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf<n>/stop

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		This file allows to control scheduling of the VF on the Intel Xe GPU

		platforms. It allows to implement custom policy mechanism in case VFs

		are misbehaving or triggering adverse events above defined thresholds.



		stop: (WO) bool

			All GT executions of given function shall be immediately stopped.

			To allow scheduling this VF again, the VF FLR must be triggered.



		Writes to this attribute may fail with errors like:

			-EINVAL if provided input is malformed or not recognized,

			-EPERM if change is not applicable on given HW/FW,

			-EIO if FW refuses to change the scheduling.





What:		/sys/bus/pci/drivers/xe/.../sriov_admin/pf/device

What:		/sys/bus/pci/drivers/xe/.../sriov_admin/vf<n>/device

Date:		October 2025

KernelVersion:	6.19

Contact:	intel-xe@lists.freedesktop.org

Description:

		These are symlinks to the underlying PCI device entry representing

		given Xe SR-IOV function. For the PF, this link is always present.

		For VFs, this link is present only for currently enabled VFs.

Documentation/gpu/xe/xe_gt_freq.rst

+3 −0
Original line number Diff line number Diff line
@@ -7,6 +7,9 @@ Xe GT Frequency Management 
.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_freq.c

   :doc: Xe GT Frequency Management



.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_throttle.c

   :doc: Xe GT Throttle



Internal API

============

drivers/gpu/drm/xe/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -58,7 +58,6 @@ xe-y += xe_bb.o \ 
	xe_gt_freq.o \

	xe_gt_idle.o \

	xe_gt_mcr.o \

	xe_gt_pagefault.o \

	xe_gt_sysfs.o \

	xe_gt_throttle.o \

	xe_gt_topology.o \
@@ -73,6 +72,7 @@ xe-y += xe_bb.o \ 
	xe_guc_id_mgr.o \

	xe_guc_klv_helpers.o \

	xe_guc_log.o \

	xe_guc_pagefault.o \

	xe_guc_pc.o \

	xe_guc_submit.o \

	xe_guc_tlb_inval.o \
@@ -94,6 +94,7 @@ xe-y += xe_bb.o \ 
	xe_nvm.o \

	xe_oa.o \

	xe_observation.o \

	xe_pagefault.o \

	xe_pat.o \

	xe_pci.o \

	xe_pcode.o \
@@ -178,6 +179,7 @@ xe-$(CONFIG_PCI_IOV) += \ 
	xe_sriov_pf_debugfs.o \

	xe_sriov_pf_provision.o \

	xe_sriov_pf_service.o \

	xe_sriov_pf_sysfs.o \

	xe_tile_sriov_pf_debugfs.o



# include helpers for tests even when XE is built-in

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+13 −0
Original line number Diff line number Diff line
@@ -590,6 +590,7 @@ 
#define GT_GFX_RC6				XE_REG(0x138108)



#define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)

/* Common performance limit reason bits - available on all platforms */

#define   GT0_PERF_LIMIT_REASONS_MASK		0xde3

#define   PROCHOT_MASK				REG_BIT(0)

#define   THERMAL_LIMIT_MASK			REG_BIT(1)
@@ -599,6 +600,18 @@ 
#define   POWER_LIMIT_4_MASK			REG_BIT(8)

#define   POWER_LIMIT_1_MASK			REG_BIT(10)

#define   POWER_LIMIT_2_MASK			REG_BIT(11)

/* Platform-specific performance limit reason bits - for Crescent Island */

#define   CRI_PERF_LIMIT_REASONS_MASK		0xfdff

#define   SOC_THERMAL_LIMIT_MASK		REG_BIT(1)

#define   MEM_THERMAL_MASK			REG_BIT(2)

#define   VR_THERMAL_MASK			REG_BIT(3)

#define   ICCMAX_MASK				REG_BIT(4)

#define   SOC_AVG_THERMAL_MASK			REG_BIT(6)

#define   FASTVMODE_MASK			REG_BIT(7)

#define   PSYS_PL1_MASK				REG_BIT(12)

#define   PSYS_PL2_MASK				REG_BIT(13)

#define   P0_FREQ_MASK				REG_BIT(14)

#define   PSYS_CRIT_MASK			REG_BIT(15)



#define GT_PERF_STATUS				XE_REG(0x1381b4)

#define   VOLTAGE_MASK				REG_GENMASK(10, 0)

drivers/gpu/drm/xe/regs/xe_pmt.h

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)

#define BMG_G2_RESIDENCY_OFFSET		(0x530)

#define BMG_G6_RESIDENCY_OFFSET		(0x538)

#define BMG_G7_RESIDENCY_OFFSET		(0x4B0)

#define BMG_G8_RESIDENCY_OFFSET		(0x540)

#define BMG_G10_RESIDENCY_OFFSET		(0x548)