Commit 6196fe77 authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

arm64: dts: imx8qxp: add GPU nodes 



Add the DT node for the GPU core found on the i.MX8QXP.

etnaviv-gpu 53100000.gpu: model: GC7000, revision: 6214
[drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5136ea6b

arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi

0 → 100644
+27 −0
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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019 NXP

 *	Dong Aisheng <aisheng.dong@nxp.com>

 */



#include <dt-bindings/firmware/imx/rsrc.h>



gpu0_subsys: bus@53000000 {

	compatible = "simple-bus";

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0x53000000 0x0 0x53000000 0x1000000>;



	gpu_3d0: gpu@53100000 {

		compatible = "vivante,gc";

		reg = <0x53100000 0x40000>;

		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,

			 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;

		clock-names = "core", "shader";

		assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,

				  <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;

		assigned-clock-rates = <700000000>, <850000000>;

		power-domains = <&pd IMX_SC_R_GPU_0_PID0>;

	};

};

arch/arm64/boot/dts/freescale/imx8qxp.dtsi

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@@ -317,6 +317,7 @@ map0 { 
	/* sorted in register address */

	#include "imx8-ss-img.dtsi"

	#include "imx8-ss-vpu.dtsi"

	#include "imx8-ss-gpu0.dtsi"

	#include "imx8-ss-adma.dtsi"

	#include "imx8-ss-conn.dtsi"

	#include "imx8-ss-ddr.dtsi"