Commit 61acc442 authored by Abhash Kumar Jha's avatar Abhash Kumar Jha Committed by Nishanth Menon
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arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for j784s4 



Each A72 core has one watchdog instance associated with it. Since j742s2
has 4 A72 cores, the common file should not define 8 watchdog instances.

Refactor the last 4 extra watchdogs from the common file to j784s4
specific file, as j784s4 has 8 A72 cores and thus hardware description
requires 8 watchdog instances.

Fixes: 9cc161a4 ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
Signed-off-by: default avatarAbhash Kumar Jha <a-kumar2@ti.com>
Reviewed-by: default avatarUdit Kumar <u-kumar1@ti.com>
Link: https://patch.msgid.link/20260112085113.3476193-3-a-kumar2@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent 24c9d5fb

arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi

+0 −36
Original line number Diff line number Diff line
@@ -2378,42 +2378,6 @@ watchdog3: watchdog@2230000 { 
		assigned-clock-parents = <&k3_clks 351 4>;

	};



	watchdog4: watchdog@2240000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2240000 0x00 0x100>;

		clocks = <&k3_clks 352 0>;

		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 352 0>;

		assigned-clock-parents = <&k3_clks 352 4>;

	};



	watchdog5: watchdog@2250000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2250000 0x00 0x100>;

		clocks = <&k3_clks 353 0>;

		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 353 0>;

		assigned-clock-parents = <&k3_clks 353 4>;

	};



	watchdog6: watchdog@2260000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2260000 0x00 0x100>;

		clocks = <&k3_clks 354 0>;

		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 354 0>;

		assigned-clock-parents = <&k3_clks 354 4>;

	};



	watchdog7: watchdog@2270000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2270000 0x00 0x100>;

		clocks = <&k3_clks 355 0>;

		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 355 0>;

		assigned-clock-parents = <&k3_clks 355 4>;

	};



	/*

	 * The following RTI instances are coupled with MCU R5Fs, c7x and

	 * GPU so keeping them reserved as these will be used by their

arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -6,6 +6,42 @@ 
 */



&cbass_main {

	watchdog4: watchdog@2240000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2240000 0x00 0x100>;

		clocks = <&k3_clks 352 0>;

		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 352 0>;

		assigned-clock-parents = <&k3_clks 352 4>;

	};



	watchdog5: watchdog@2250000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2250000 0x00 0x100>;

		clocks = <&k3_clks 353 0>;

		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 353 0>;

		assigned-clock-parents = <&k3_clks 353 4>;

	};



	watchdog6: watchdog@2260000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2260000 0x00 0x100>;

		clocks = <&k3_clks 354 0>;

		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 354 0>;

		assigned-clock-parents = <&k3_clks 354 4>;

	};



	watchdog7: watchdog@2270000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2270000 0x00 0x100>;

		clocks = <&k3_clks 355 0>;

		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 355 0>;

		assigned-clock-parents = <&k3_clks 355 4>;

	};



	pcie2_rc: pcie@2920000 {

		compatible = "ti,j784s4-pcie-host";

		reg = <0x00 0x02920000 0x00 0x1000>,