Commit 61ebeecb authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

rtw89: add chip_ops::{enable,disable}_bb_rf to support v1 chip



The v1 chip use specific functions to enable and disable BB/RF.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-11-pkshih@realtek.com
parent cf7b8b80
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+5 −2
Original line number Diff line number Diff line
@@ -2706,8 +2706,11 @@ int rtw89_core_start(struct rtw89_dev *rtwdev)
	/* efuse process */

	/* pre-config BB/RF, BB reset/RFC reset */
	rtw89_mac_disable_bb_rf(rtwdev);
	rtw89_mac_enable_bb_rf(rtwdev);
	rtw89_chip_disable_bb_rf(rtwdev);
	ret = rtw89_chip_enable_bb_rf(rtwdev);
	if (ret)
		return ret;

	rtw89_phy_init_bb_reg(rtwdev);
	rtw89_phy_init_rf_reg(rtwdev);

+2 −0
Original line number Diff line number Diff line
@@ -2059,6 +2059,8 @@ struct rtw89_hci_info {
};

struct rtw89_chip_ops {
	int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
	void (*disable_bb_rf)(struct rtw89_dev *rtwdev);
	void (*bb_reset)(struct rtw89_dev *rtwdev,
			 enum rtw89_phy_idx phy_idx);
	void (*bb_sethw)(struct rtw89_dev *rtwdev);
+8 −2
Original line number Diff line number Diff line
@@ -2828,7 +2828,7 @@ static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev)
			  B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
}

void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
{
	rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
@@ -2836,7 +2836,10 @@ void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
			  B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
			  B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
	rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);

	return 0;
}
EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);

void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
{
@@ -2847,6 +2850,7 @@ void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
			  B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
	rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
}
EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);

int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)
{
@@ -2892,7 +2896,9 @@ int rtw89_mac_init(struct rtw89_dev *rtwdev)
	if (ret)
		goto fail;

	rtw89_mac_enable_bb_rf(rtwdev);
	ret = rtw89_chip_enable_bb_rf(rtwdev);
	if (ret)
		goto fail;

	ret = rtw89_mac_sys_init(rtwdev);
	if (ret)
+18 −1
Original line number Diff line number Diff line
@@ -797,8 +797,23 @@ int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);

static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
{
	const struct rtw89_chip_info *chip = rtwdev->chip;

	return chip->ops->enable_bb_rf(rtwdev);
}

static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
{
	const struct rtw89_chip_info *chip = rtwdev->chip;

	chip->ops->disable_bb_rf(rtwdev);
}

u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
@@ -903,6 +918,8 @@ int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
				 struct rtw89_sta *rtwsta, u8 *tx_retry);

enum rtw89_mac_xtal_si_offset {
	XTAL0 = 0x0,
	XTAL3 = 0x3,
	XTAL_SI_XTAL_SC_XI = 0x04,
#define XTAL_SC_XI_MASK		GENMASK(7, 0)
	XTAL_SI_XTAL_SC_XO = 0x05,
+6 −0
Original line number Diff line number Diff line
@@ -218,6 +218,7 @@
#define B_AX_EECS_PULL_LOW_EN BIT(16)

#define R_AX_WLRF_CTRL 0x02F0
#define B_AX_AFC_AFEDIG BIT(17)
#define B_AX_WLRF1_CTRL_7 BIT(15)
#define B_AX_WLRF1_CTRL_1 BIT(9)
#define B_AX_WLRF_CTRL_7 BIT(7)
@@ -231,6 +232,11 @@
#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)

#define R_AX_AFE_OFF_CTRL1 0x0444
#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
#define B_AX_S1_LDO2PWRCUT_F BIT(23)
#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)

#define R_AX_FILTER_MODEL_ADDR 0x0C04

#define R_AX_HAXI_INIT_CFG1 0x1000
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