Commit 61f2e8a3 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz 



CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
250/333/500/1000MHz in fact.

The PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d6 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: default avatarHal Feng <hal.feng@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 591940e2

arch/riscv/boot/dts/starfive/jh7110-common.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -365,6 +365,12 @@ spi_dev0: spi@0 { 
	};

};



&syscrg {

	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,

			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;

	assigned-clock-rates = <500000000>, <1500000000>;

};



&sysgpio {

	i2c0_pins: i2c0-0 {

		i2c-pins {