Commit 61fbfac1 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'mt7530-dsa-subdriver-fix-vlan-egress-and-handling-of-all-link-local-frames' 



 says:

====================
MT7530 DSA subdriver fix VLAN egress and handling of all link-local frames

This patch series fixes the VLAN tag egress procedure for link-local
frames, and fixes handling of all link-local frames.

Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
====================

Link: https://lore.kernel.org/r/20240314-b4-for-net-mt7530-fix-link-local-vlan-v2-0-7dbcf6429ba0@arinc9.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 3201de46 69ddba9d

drivers/net/dsa/mt7530.c

+44 −8
Original line number Diff line number Diff line
@@ -950,20 +950,56 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 
	mutex_unlock(&priv->reg_mutex);

}



/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std

 * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA

 * must only be propagated to C-VLAN and MAC Bridge components. That means

 * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,

 * these frames are supposed to be processed by the CPU (software). So we make

 * the switch only forward them to the CPU port. And if received from a CPU

 * port, forward to a single port. The software is responsible of making the

 * switch conform to the latter by setting a single port as destination port on

 * the special tag.

 *

 * This switch intellectual property cannot conform to this part of the standard

 * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC

 * DAs, it also includes :22-FF which the scope of propagation is not supposed

 * to be restricted for these MAC DAs.

 */

static void

mt753x_trap_frames(struct mt7530_priv *priv)

{

	/* Trap BPDUs to the CPU port(s) */

	mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,

	/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them

	 * VLAN-untagged.

	 */

	mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |

		   MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |

		   MT753X_BPDU_PORT_FW_MASK,

		   MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |

		   MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |

		   MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |

		   MT753X_BPDU_CPU_ONLY);



	/* Trap 802.1X PAE frames to the CPU port(s) */

	mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_PORT_FW_MASK,

		   MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY));

	/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress

	 * them VLAN-untagged.

	 */

	mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |

		   MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |

		   MT753X_R01_PORT_FW_MASK,

		   MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |

		   MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |

		   MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |

		   MT753X_BPDU_CPU_ONLY);



	/* Trap LLDP frames with :0E MAC DA to the CPU port(s) */

	mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK,

		   MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY));

	/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress

	 * them VLAN-untagged.

	 */

	mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |

		   MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |

		   MT753X_R03_PORT_FW_MASK,

		   MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |

		   MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |

		   MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |

		   MT753X_BPDU_CPU_ONLY);

}



static void

drivers/net/dsa/mt7530.h

+21 −1
Original line number Diff line number Diff line
@@ -65,14 +65,33 @@ enum mt753x_id { 


/* Registers for BPDU and PAE frame control*/

#define MT753X_BPC			0x24

#define  MT753X_BPDU_PORT_FW_MASK	GENMASK(2, 0)

#define  MT753X_PAE_EG_TAG_MASK		GENMASK(24, 22)

#define  MT753X_PAE_EG_TAG(x)		FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)

#define  MT753X_PAE_PORT_FW_MASK	GENMASK(18, 16)

#define  MT753X_PAE_PORT_FW(x)		FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)

#define  MT753X_BPDU_EG_TAG_MASK	GENMASK(8, 6)

#define  MT753X_BPDU_EG_TAG(x)		FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)

#define  MT753X_BPDU_PORT_FW_MASK	GENMASK(2, 0)



/* Register for :01 and :02 MAC DA frame control */

#define MT753X_RGAC1			0x28

#define  MT753X_R02_EG_TAG_MASK		GENMASK(24, 22)

#define  MT753X_R02_EG_TAG(x)		FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)

#define  MT753X_R02_PORT_FW_MASK	GENMASK(18, 16)

#define  MT753X_R02_PORT_FW(x)		FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)

#define  MT753X_R01_EG_TAG_MASK		GENMASK(8, 6)

#define  MT753X_R01_EG_TAG(x)		FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)

#define  MT753X_R01_PORT_FW_MASK	GENMASK(2, 0)



/* Register for :03 and :0E MAC DA frame control */

#define MT753X_RGAC2			0x2c

#define  MT753X_R0E_EG_TAG_MASK		GENMASK(24, 22)

#define  MT753X_R0E_EG_TAG(x)		FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)

#define  MT753X_R0E_PORT_FW_MASK	GENMASK(18, 16)

#define  MT753X_R0E_PORT_FW(x)		FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)

#define  MT753X_R03_EG_TAG_MASK		GENMASK(8, 6)

#define  MT753X_R03_EG_TAG(x)		FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)

#define  MT753X_R03_PORT_FW_MASK	GENMASK(2, 0)



enum mt753x_bpdu_port_fw {

	MT753X_BPDU_FOLLOW_MFC,
@@ -253,6 +272,7 @@ enum mt7530_port_mode { 
enum mt7530_vlan_port_eg_tag {

	MT7530_VLAN_EG_DISABLED = 0,

	MT7530_VLAN_EG_CONSISTENT = 1,

	MT7530_VLAN_EG_UNTAGGED = 4,

};



enum mt7530_vlan_port_attr {