Commit 62120d81 authored by Varada Pavani's avatar Varada Pavani Committed by Krzysztof Kozlowski
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clk: samsung: Use samsung CCF common function 



Use samsung CCF function which registers multiple clock providers using
single function call samsung_cmu_register_clocks().

Signed-off-by: default avatarVarada Pavani <v.pavani@samsung.com>
Link: https://lore.kernel.org/r/20250307092403.19742-1-v.pavani@samsung.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 0af2f6be

drivers/clk/samsung/clk-exynos4.c

+42 −32
Original line number Diff line number Diff line
@@ -1269,6 +1269,45 @@ static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = { 
		CPUCLK_LAYOUT_E4210, e4412_armclk_d),

};



static const struct samsung_cmu_info cmu_info_exynos4 __initconst = {

	.mux_clks		= exynos4_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(exynos4_mux_clks),

	.div_clks		= exynos4_div_clks,

	.nr_div_clks		= ARRAY_SIZE(exynos4_div_clks),

	.gate_clks		= exynos4_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(exynos4_gate_clks),

	.fixed_factor_clks	= exynos4_fixed_factor_clks,

	.nr_fixed_factor_clks	= ARRAY_SIZE(exynos4_fixed_factor_clks),

	.fixed_clks	= exynos4_fixed_rate_clks,

	.nr_fixed_clks	= ARRAY_SIZE(exynos4_fixed_rate_clks),

};



static const struct samsung_cmu_info cmu_info_exynos4210 __initconst = {

	.mux_clks		= exynos4210_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(exynos4210_mux_clks),

	.div_clks		= exynos4210_div_clks,

	.nr_div_clks		= ARRAY_SIZE(exynos4210_div_clks),

	.gate_clks		= exynos4210_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(exynos4210_gate_clks),

	.fixed_factor_clks	= exynos4210_fixed_factor_clks,

	.nr_fixed_factor_clks	= ARRAY_SIZE(exynos4210_fixed_factor_clks),

	.fixed_clks	= exynos4210_fixed_rate_clks,

	.nr_fixed_clks	= ARRAY_SIZE(exynos4210_fixed_rate_clks),

	.cpu_clks		= exynos4210_cpu_clks,

	.nr_cpu_clks		= ARRAY_SIZE(exynos4210_cpu_clks),

};



static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst = {

	.mux_clks		= exynos4x12_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(exynos4x12_mux_clks),

	.div_clks		= exynos4x12_div_clks,

	.nr_div_clks		= ARRAY_SIZE(exynos4x12_div_clks),

	.gate_clks		= exynos4x12_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(exynos4x12_gate_clks),

	.fixed_factor_clks	= exynos4x12_fixed_factor_clks,

	.nr_fixed_factor_clks	= ARRAY_SIZE(exynos4x12_fixed_factor_clks),

};



/* register exynos4 clocks */

static void __init exynos4_clk_init(struct device_node *np,

				    enum exynos4_soc soc)
@@ -1322,41 +1361,12 @@ static void __init exynos4_clk_init(struct device_node *np, 
					ARRAY_SIZE(exynos4x12_plls));

	}



	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,

			ARRAY_SIZE(exynos4_fixed_rate_clks));

	samsung_clk_register_mux(ctx, exynos4_mux_clks,

			ARRAY_SIZE(exynos4_mux_clks));

	samsung_clk_register_div(ctx, exynos4_div_clks,

			ARRAY_SIZE(exynos4_div_clks));

	samsung_clk_register_gate(ctx, exynos4_gate_clks,

			ARRAY_SIZE(exynos4_gate_clks));

	samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,

			ARRAY_SIZE(exynos4_fixed_factor_clks));

	samsung_cmu_register_clocks(ctx, &cmu_info_exynos4);



	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,

			ARRAY_SIZE(exynos4210_fixed_rate_clks));

		samsung_clk_register_mux(ctx, exynos4210_mux_clks,

			ARRAY_SIZE(exynos4210_mux_clks));

		samsung_clk_register_div(ctx, exynos4210_div_clks,

			ARRAY_SIZE(exynos4210_div_clks));

		samsung_clk_register_gate(ctx, exynos4210_gate_clks,

			ARRAY_SIZE(exynos4210_gate_clks));

		samsung_clk_register_fixed_factor(ctx,

			exynos4210_fixed_factor_clks,

			ARRAY_SIZE(exynos4210_fixed_factor_clks));

		samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,

				ARRAY_SIZE(exynos4210_cpu_clks));

		samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210);

	} else {

		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,

			ARRAY_SIZE(exynos4x12_mux_clks));

		samsung_clk_register_div(ctx, exynos4x12_div_clks,

			ARRAY_SIZE(exynos4x12_div_clks));

		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,

			ARRAY_SIZE(exynos4x12_gate_clks));

		samsung_clk_register_fixed_factor(ctx,

			exynos4x12_fixed_factor_clks,

			ARRAY_SIZE(exynos4x12_fixed_factor_clks));

		samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12);

		if (soc == EXYNOS4412)

			samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,

					ARRAY_SIZE(exynos4412_cpu_clks));