Commit 6216fb03 authored by Ajit Pal Singh's avatar Ajit Pal Singh Committed by Jeff Hugo
Browse files

accel/qaic: Add support for periodic timesync



Device and Host have a time synchronization mechanism that happens once
during boot when device is in SBL mode. After that, in mission-mode there
is no timesync. In an experiment after continuous operation, device time
drifted w.r.t. host by approximately 3 seconds per day. This drift leads
to mismatch in timestamp of device and Host logs. To correct this
implement periodic timesync in driver. This timesync is carried out via
QAIC_TIMESYNC_PERIODIC MHI channel.

Signed-off-by: default avatarAjit Pal Singh <quic_ajitpals@quicinc.com>
Signed-off-by: default avatarPranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
Reviewed-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: default avatarCarl Vanderlip <quic_carlv@quicinc.com>
Reviewed-by: default avatarPranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
Signed-off-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: default avatarStanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231016170114.5446-2-quic_jhugo@quicinc.com
parent bb8e97e2
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+4 −0
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@@ -225,6 +225,10 @@ of the defined channels, and their uses.
|                |         |          | device side logs with the host time    |
|                |         |          | source.                                |
+----------------+---------+----------+----------------------------------------+
| QAIC_TIMESYNC  | 22 & 23 | AMSS     | Used to periodically synchronize       |
| _PERIODIC      |         |          | timestamps in the device side logs with|
|                |         |          | the host time source.                  |
+----------------+---------+----------+----------------------------------------+

DMA Bridge
==========
+5 −0
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@@ -201,3 +201,8 @@ overrides this for that call. Default is 5000 (5 seconds).

Sets the polling interval in microseconds (us) when datapath polling is active.
Takes effect at the next polling interval. Default is 100 (100 us).

**timesync_delay_ms (unsigned int)**

Sets the time interval in milliseconds (ms) between two consecutive timesync
operations. Default is 1000 (1000 ms).
+2 −1
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@@ -9,4 +9,5 @@ qaic-y := \
	mhi_controller.o \
	qaic_control.o \
	qaic_data.o \
	qaic_drv.o
	qaic_drv.o \
	qaic_timesync.o
+32 −0
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@@ -373,6 +373,38 @@ static struct mhi_channel_config aic100_channels[] = {
		.auto_queue = false,
		.wake_capable = false,
	},
	{
		.name = "QAIC_TIMESYNC_PERIODIC",
		.num = 22,
		.num_elements = 32,
		.local_elements = 0,
		.event_ring = 0,
		.dir = DMA_TO_DEVICE,
		.ee_mask = MHI_CH_EE_AMSS,
		.pollcfg = 0,
		.doorbell = MHI_DB_BRST_DISABLE,
		.lpm_notify = false,
		.offload_channel = false,
		.doorbell_mode_switch = false,
		.auto_queue = false,
		.wake_capable = false,
	},
	{
		.num = 23,
		.name = "QAIC_TIMESYNC_PERIODIC",
		.num_elements = 32,
		.local_elements = 0,
		.event_ring = 0,
		.dir = DMA_FROM_DEVICE,
		.ee_mask = MHI_CH_EE_AMSS,
		.pollcfg = 0,
		.doorbell = MHI_DB_BRST_DISABLE,
		.lpm_notify = false,
		.offload_channel = false,
		.doorbell_mode_switch = false,
		.auto_queue = false,
		.wake_capable = false,
	},
};

static struct mhi_event_config aic100_events[] = {
+6 −0
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@@ -27,6 +27,7 @@

#include "mhi_controller.h"
#include "qaic.h"
#include "qaic_timesync.h"

MODULE_IMPORT_NS(DMA_BUF);

@@ -599,6 +600,10 @@ static int __init qaic_init(void)
		goto free_pci;
	}

	ret = qaic_timesync_init();
	if (ret)
		pr_debug("qaic: qaic_timesync_init failed %d\n", ret);

	return 0;

free_pci:
@@ -624,6 +629,7 @@ static void __exit qaic_exit(void)
	 * reinitializing the link_up state after the cleanup is done.
	 */
	link_up = true;
	qaic_timesync_deinit();
	mhi_driver_unregister(&qaic_mhi_driver);
	pci_unregister_driver(&qaic_pci_driver);
}
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