Commit 621ba4d9 authored by Yao Zi's avatar Yao Zi Committed by Heiko Stuebner
Browse files

clk: rockchip: Support MMC clocks in GRF region 



Registers of MMC drive/sample clocks in Rockchip RV1106 and RK3528
locate in GRF regions. Adjust MMC clock code to support register
operations through regmap.

Signed-off-by: default avatarYao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250506092206.46143-3-ziyao@disroot.org


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 58883d58

drivers/clk/rockchip/clk-mmc-phase.c

+20 −4
Original line number Diff line number Diff line
@@ -9,11 +9,14 @@ 
#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/regmap.h>

#include "clk.h"



struct rockchip_mmc_clock {

	struct clk_hw	hw;

	void __iomem	*reg;

	struct regmap	*grf;

	int		grf_reg;

	int		shift;

	int		cached_phase;

	struct notifier_block clk_rate_change_nb;
@@ -54,7 +57,12 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) 
	if (!rate)

		return 0;



	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);

	if (mmc_clock->grf)

		regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value);

	else

		raw_value = readl(mmc_clock->reg);



	raw_value >>= mmc_clock->shift;



	degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
@@ -134,8 +142,12 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) 
	raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;

	raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;

	raw_value |= nineties;

	writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),

	       mmc_clock->reg);

	raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift);



	if (mmc_clock->grf)

		regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value);

	else

		writel(raw_value, mmc_clock->reg);



	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",

		clk_hw_get_name(hw), degrees, delay_num,
@@ -189,7 +201,9 @@ static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb, 


struct clk *rockchip_clk_register_mmc(const char *name,

				const char *const *parent_names, u8 num_parents,

				void __iomem *reg, int shift)

				void __iomem *reg,

				struct regmap *grf, int grf_reg,

				int shift)

{

	struct clk_init_data init;

	struct rockchip_mmc_clock *mmc_clock;
@@ -208,6 +222,8 @@ struct clk *rockchip_clk_register_mmc(const char *name, 


	mmc_clock->hw.init = &init;

	mmc_clock->reg = reg;

	mmc_clock->grf = grf;

	mmc_clock->grf_reg = grf_reg;

	mmc_clock->shift = shift;



	clk = clk_register(NULL, &mmc_clock->hw);

drivers/clk/rockchip/clk.c

+14 −2
Original line number Diff line number Diff line
@@ -509,7 +509,9 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 
		clk = NULL;



		/* for GRF-dependent branches, choose the right grf first */

		if ((list->branch_type == branch_muxgrf || list->branch_type == branch_grf_gate) &&

		if ((list->branch_type == branch_muxgrf ||

		     list->branch_type == branch_grf_gate ||

		     list->branch_type == branch_grf_mmc) &&

		    list->grf_type != grf_type_sys) {

			hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {

				if (agrf->type == list->grf_type) {
@@ -612,6 +614,16 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 
				list->name,

				list->parent_names, list->num_parents,

				ctx->reg_base + list->muxdiv_offset,

				NULL, 0,

				list->div_shift

			);

			break;

		case branch_grf_mmc:

			clk = rockchip_clk_register_mmc(

				list->name,

				list->parent_names, list->num_parents,

				0,

				grf, list->muxdiv_offset,

				list->div_shift

			);

			break;

drivers/clk/rockchip/clk.h

+16 −1
Original line number Diff line number Diff line
@@ -619,7 +619,9 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, 


struct clk *rockchip_clk_register_mmc(const char *name,

				const char *const *parent_names, u8 num_parents,

				void __iomem *reg, int shift);

				void __iomem *reg,

				struct regmap *grf, int grf_reg,

				int shift);



/*

 * DDRCLK flags, including method of setting the rate
@@ -664,6 +666,7 @@ enum rockchip_clk_branch_type { 
	branch_grf_gate,

	branch_linked_gate,

	branch_mmc,

	branch_grf_mmc,

	branch_inverter,

	branch_factor,

	branch_ddrclk,
@@ -1030,6 +1033,18 @@ struct rockchip_clk_branch { 
		.div_shift	= shift,			\

	}



#define MMC_GRF(_id, cname, pname, offset, shift, grftype)	\

	{							\

		.id		= _id,				\

		.branch_type	= branch_grf_mmc,		\

		.name		= cname,			\

		.parent_names	= (const char *[]){ pname },	\

		.num_parents	= 1,				\

		.muxdiv_offset	= offset,			\

		.div_shift	= shift,			\

		.grf_type	= grftype,			\

	}



#define INVERTER(_id, cname, pname, io, is, if)			\

	{							\

		.id		= _id,				\