Commit 626737a5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pin control fixes from Linus Walleij:

 - Use flag saving spinlocks in the Renesas rzg2l driver. This fixes up
   PREEMPT_RT problems.

 - Remove broken Qualcomm PM8008 that clearly was never working. A new
   version will arrive in the next merge window.

 - Add a quirk for LP8764 regmap that was missed and made the TI J7200
   board unusable.

 - Fix persistance on the BCM2835 GPIO outputs kernel parameter so this
   remains consisten across a booted kernel.

 - Fix a potential deadlock in create_pinctrl()

 - Fix some erroneous bitfields and pinmux reset in the Rockchip RK3328
   driver.

* tag 'pinctrl-v6.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set
  pinctrl: rockchip: use dedicated pinctrl type for RK3328
  pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins
  pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins
  pinctrl: fix deadlock in create_pinctrl() when handling -EPROBE_DEFER
  pinctrl: bcm2835: Fix permissions of persist_gpio_outputs
  pinctrl: tps6594: add missing support for LP8764 PMIC
  dt-bindings: pinctrl: qcom,pmic-gpio: drop pm8008
  pinctrl: qcom: spmi-gpio: drop broken pm8008 support
  pinctrl: renesas: rzg2l: Use spin_{lock,unlock}_irq{save,restore}
parents f2661062 4ea4d480
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+0 −3
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ properties:
          - qcom,pm7325-gpio
          - qcom,pm7550ba-gpio
          - qcom,pm8005-gpio
          - qcom,pm8008-gpio
          - qcom,pm8018-gpio
          - qcom,pm8019-gpio
          - qcom,pm8038-gpio
@@ -126,7 +125,6 @@ allOf:
        compatible:
          contains:
            enum:
              - qcom,pm8008-gpio
              - qcom,pmi8950-gpio
              - qcom,pmr735d-gpio
    then:
@@ -448,7 +446,6 @@ $defs:
                 - gpio1-gpio10 for pm7325
                 - gpio1-gpio8 for pm7550ba
                 - gpio1-gpio4 for pm8005
                 - gpio1-gpio2 for pm8008
                 - gpio1-gpio6 for pm8018
                 - gpio1-gpio12 for pm8038
                 - gpio1-gpio40 for pm8058
+1 −1
Original line number Diff line number Diff line
@@ -245,7 +245,7 @@ static const char * const irq_type_names[] = {
};

static bool persist_gpio_outputs;
module_param(persist_gpio_outputs, bool, 0644);
module_param(persist_gpio_outputs, bool, 0444);
MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed");

static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
+1 −1
Original line number Diff line number Diff line
@@ -1106,8 +1106,8 @@ static struct pinctrl *create_pinctrl(struct device *dev,
		 * an -EPROBE_DEFER later, as that is the worst case.
		 */
		if (ret == -EPROBE_DEFER) {
			pinctrl_free(p, false);
			mutex_unlock(&pinctrl_maps_mutex);
			pinctrl_free(p, false);
			return ERR_PTR(ret);
		}
	}
+59 −9
Original line number Diff line number Diff line
@@ -634,23 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {

static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
	{
		.num = 2,
		.pin = 12,
		.reg = 0x24,
		.bit = 8,
		.mask = 0x3
	}, {
		/* gpio2_b7_sel */
		.num = 2,
		.pin = 15,
		.reg = 0x28,
		.bit = 0,
		.mask = 0x7
	}, {
		/* gpio2_c7_sel */
		.num = 2,
		.pin = 23,
		.reg = 0x30,
		.bit = 14,
		.mask = 0x3
	}, {
		/* gpio3_b1_sel */
		.num = 3,
		.pin = 9,
		.reg = 0x44,
		.bit = 2,
		.mask = 0x3
	}, {
		/* gpio3_b2_sel */
		.num = 3,
		.pin = 10,
		.reg = 0x44,
		.bit = 4,
		.mask = 0x3
	}, {
		/* gpio3_b3_sel */
		.num = 3,
		.pin = 11,
		.reg = 0x44,
		.bit = 6,
		.mask = 0x3
	}, {
		/* gpio3_b4_sel */
		.num = 3,
		.pin = 12,
		.reg = 0x44,
		.bit = 8,
		.mask = 0x3
	}, {
		/* gpio3_b5_sel */
		.num = 3,
		.pin = 13,
		.reg = 0x44,
		.bit = 10,
		.mask = 0x3
	}, {
		/* gpio3_b6_sel */
		.num = 3,
		.pin = 14,
		.reg = 0x44,
		.bit = 12,
		.mask = 0x3
	}, {
		/* gpio3_b7_sel */
		.num = 3,
		.pin = 15,
		.reg = 0x44,
		.bit = 14,
		.mask = 0x3
	},
};

@@ -2433,6 +2478,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
	case RK3188:
	case RK3288:
	case RK3308:
	case RK3328:
	case RK3368:
	case RK3399:
	case RK3568:
@@ -2491,6 +2537,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
	case RK3188:
	case RK3288:
	case RK3308:
	case RK3328:
	case RK3368:
	case RK3399:
	case RK3568:
@@ -2704,8 +2751,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,

	if (ret) {
		/* revert the already done pin settings */
		for (cnt--; cnt >= 0; cnt--)
		for (cnt--; cnt >= 0; cnt--) {
			bank = pin_to_bank(info, pins[cnt]);
			rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
		}

		return ret;
	}
@@ -2753,6 +2802,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
	case RK3188:
	case RK3288:
	case RK3308:
	case RK3328:
	case RK3368:
	case RK3399:
	case RK3568:
@@ -3763,7 +3813,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
			     IOMUX_WIDTH_3BIT,
			     0,
			     IOMUX_WIDTH_3BIT,
			     0),
	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
@@ -3777,7 +3827,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
		.pin_banks		= rk3328_pin_banks,
		.nr_banks		= ARRAY_SIZE(rk3328_pin_banks),
		.label			= "RK3328-GPIO",
		.type			= RK3288,
		.type			= RK3328,
		.grf_mux_offset		= 0x0,
		.iomux_recalced		= rk3328_mux_recalced_data,
		.niomux_recalced	= ARRAY_SIZE(rk3328_mux_recalced_data),
+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ enum rockchip_pinctrl_type {
	RK3188,
	RK3288,
	RK3308,
	RK3328,
	RK3368,
	RK3399,
	RK3568,
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