Commit 62889b6a authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'nte-stmmac-visconti-cleanups' 

Russell King says:

====================
net: stmmac: visconti: cleanups

A short series of cleanups to the visconti dwmac glue.
====================

Link: https://patch.msgid.link/aFCHJWXSLbUoogi6@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 01c559c8 d54d42a4

drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c

+74 −55
Original line number Diff line number Diff line
@@ -48,7 +48,6 @@ 


struct visconti_eth {

	void __iomem *reg;

	u32 phy_intf_sel;

	struct clk *phy_ref_clk;

	struct device *dev;

};
@@ -57,42 +56,35 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 
					phy_interface_t interface, int speed)

{

	struct visconti_eth *dwmac = bsp_priv;

	struct net_device *netdev = dev_get_drvdata(dwmac->dev);

	unsigned int val, clk_sel_val = 0;

	unsigned long clk_sel, val;



	if (phy_interface_mode_is_rgmii(interface)) {

		switch (speed) {

		case SPEED_1000:

		if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)

			clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_125M;

			clk_sel = ETHER_CLK_SEL_FREQ_SEL_125M;

			break;



		case SPEED_100:

		if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)

			clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_25M;

		if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII)

			clk_sel_val = ETHER_CLK_SEL_DIV_SEL_2;

			clk_sel = ETHER_CLK_SEL_FREQ_SEL_25M;

			break;



		case SPEED_10:

		if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)

			clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_2P5M;

		if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII)

			clk_sel_val = ETHER_CLK_SEL_DIV_SEL_20;

			clk_sel = ETHER_CLK_SEL_FREQ_SEL_2P5M;

			break;



		default:

		/* No bit control */

		netdev_err(netdev, "Unsupported speed request (%d)", speed);

			return -EINVAL;

		}



		/* Stop internal clock */

		val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);

	val &= ~(ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN);

		val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |

			 ETHER_CLK_SEL_RX_TX_CLK_EN);

		val |= ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		/* Set Clock-Mux, Start clock, Set TX_O direction */

	switch (dwmac->phy_intf_sel) {

	case ETHER_CONFIG_INTF_RGMII:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;

		val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
@@ -100,10 +92,31 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 


		val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

	} else if (interface == PHY_INTERFACE_MODE_RMII) {

		switch (speed) {

		case SPEED_100:

			clk_sel = ETHER_CLK_SEL_DIV_SEL_2;

			break;



		case SPEED_10:

			clk_sel = ETHER_CLK_SEL_DIV_SEL_20;

			break;

	case ETHER_CONFIG_INTF_RMII:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |



		default:

			return -EINVAL;

		}



		/* Stop internal clock */

		val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);

		val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |

			 ETHER_CLK_SEL_RX_TX_CLK_EN);

		val |= ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		/* Set Clock-Mux, Start clock, Set TX_O direction */

		val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |

		      ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV |

		      ETHER_CLK_SEL_TX_O_E_N_IN |

		      ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
@@ -112,16 +125,22 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 


		val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	case ETHER_CONFIG_INTF_MII:

	default:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;

	} else {

		/* Stop internal clock */

		val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);

		val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |

			 ETHER_CLK_SEL_RX_TX_CLK_EN);

		val |= ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		/* Set Clock-Mux, Start clock, Set TX_O direction */

		val = ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |

		      ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC |

		      ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	}



	return 0;
@@ -130,28 +149,28 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, 
static int visconti_eth_init_hw(struct platform_device *pdev, struct plat_stmmacenet_data *plat_dat)

{

	struct visconti_eth *dwmac = plat_dat->bsp_priv;

	unsigned int reg_val, clk_sel_val;

	unsigned int clk_sel_val;

	u32 phy_intf_sel;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

		dwmac->phy_intf_sel = ETHER_CONFIG_INTF_RGMII;

		phy_intf_sel = ETHER_CONFIG_INTF_RGMII;

		break;

	case PHY_INTERFACE_MODE_MII:

		dwmac->phy_intf_sel = ETHER_CONFIG_INTF_MII;

		phy_intf_sel = ETHER_CONFIG_INTF_MII;

		break;

	case PHY_INTERFACE_MODE_RMII:

		dwmac->phy_intf_sel = ETHER_CONFIG_INTF_RMII;

		phy_intf_sel = ETHER_CONFIG_INTF_RMII;

		break;

	default:

		dev_err(&pdev->dev, "Unsupported phy-mode (%d)\n", plat_dat->phy_interface);

		return -EOPNOTSUPP;

	}



	reg_val = dwmac->phy_intf_sel;

	writel(reg_val, dwmac->reg + REG_ETHER_CONTROL);

	writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL);



	/* Enable TX/RX clock */

	clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_125M;
@@ -161,8 +180,8 @@ static int visconti_eth_init_hw(struct platform_device *pdev, struct plat_stmmac 
	       dwmac->reg + REG_ETHER_CLOCK_SEL);



	/* release internal-reset */

	reg_val |= ETHER_ETH_CONTROL_RESET;

	writel(reg_val, dwmac->reg + REG_ETHER_CONTROL);

	phy_intf_sel |= ETHER_ETH_CONTROL_RESET;

	writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL);



	return 0;

}