Commit 630dfec5 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Dmitry Baryshkov
Browse files

drm/msm/dsi: Add phy configuration for SM6375 



SM6375 uses a boring standard 7nm PHY. Add a configuration entry for it.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/518511/
Link: https://lore.kernel.org/r/20230116114059.346327-2-konrad.dybcio@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 454ec4a7

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −0
Original line number Diff line number Diff line
@@ -569,6 +569,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { 
	  .data = &dsi_phy_7nm_8150_cfgs },

	{ .compatible = "qcom,sc7280-dsi-phy-7nm",

	  .data = &dsi_phy_7nm_7280_cfgs },

	{ .compatible = "qcom,sm6375-dsi-phy-7nm",

	  .data = &dsi_phy_7nm_6375_cfgs },

	{ .compatible = "qcom,sm8350-dsi-phy-5nm",

	  .data = &dsi_phy_5nm_8350_cfgs },

	{ .compatible = "qcom,sm8450-dsi-phy-5nm",

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; 
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+20 −0
Original line number Diff line number Diff line
@@ -1152,6 +1152,26 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { 
	.quirks = DSI_PHY_7NM_QUIRK_V4_1,

};



const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs = {

	.has_phy_lane = true,

	.ops = {

		.enable = dsi_7nm_phy_enable,

		.disable = dsi_7nm_phy_disable,

		.pll_init = dsi_pll_7nm_init,

		.save_pll_state = dsi_7nm_pll_save_state,

		.restore_pll_state = dsi_7nm_pll_restore_state,

	},

	.min_pll_rate = 600000000UL,

#ifdef CONFIG_64BIT

	.max_pll_rate = 5000000000ULL,

#else

	.max_pll_rate = ULONG_MAX,

#endif

	.io_start = { 0x5e94400 },

	.num_dsi_phy = 1,

	.quirks = DSI_PHY_7NM_QUIRK_V4_1,

};



const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_7nm_36mA_regulators,