Commit 63180809 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.7-2023-10-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next



amd-drm-next-6.7-2023-10-27:

amdgpu:
- RAS fixes
- Seamless boot fixes
- NBIO 7.7 fix
- SMU 14.0 fixes
- GC 11.5 fixes
- DML2 fixes
- ASPM fixes
- VPE fixes
- Misc code cleanups
- SRIOV fixes
- Add some missing copyright notices
- DCN 3.5 fixes
- FAMS fixes
- Backlight fix
- S/G display fix
- fdinfo cleanups
- EXT_COHERENT fixes for APU and NUMA systems

amdkfd:
- Misc fixes
- Misc code cleanups
- SVM fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231027200343.57132-1-alexander.deucher@amd.com
parents 915b6d03 dd3dd982
Loading
Loading
Loading
Loading
+2 −1
Original line number Diff line number Diff line
@@ -104,7 +104,8 @@ amdgpu-y += \
amdgpu-y += \
	df_v1_7.o \
	df_v3_6.o \
	df_v4_3.o
	df_v4_3.o \
	df_v4_6_2.o

# add GMC block
amdgpu-y += \
+7 −2
Original line number Diff line number Diff line
@@ -1119,6 +1119,13 @@ static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
	return adev->ip_versions[ip][inst] & ~0xFFU;
}

static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
					      uint8_t ip, uint8_t inst)
{
	/* This returns full version - major/minor/rev/variant/subrevision */
	return adev->ip_versions[ip][inst];
}

static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
{
	return container_of(ddev, struct amdgpu_device, ddev);
@@ -1333,9 +1340,7 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
int amdgpu_device_pci_reset(struct amdgpu_device *adev);
bool amdgpu_device_need_post(struct amdgpu_device *adev);
bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
bool amdgpu_device_pcie_dynamic_switching_supported(void);
bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
bool amdgpu_device_aspm_support_quirk(void);

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
				  u64 num_vis_bytes);
+22 −18
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ struct amdgpu_acpi_xcc_info {
struct amdgpu_acpi_dev_info {
	struct list_head list;
	struct list_head xcc_list;
	uint16_t bdf;
	uint32_t sbdf;
	uint16_t supp_xcp_mode;
	uint16_t xcp_mode;
	uint16_t mem_mode;
@@ -927,7 +927,7 @@ static acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
#endif
}

static struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u16 bdf)
static struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u32 sbdf)
{
	struct amdgpu_acpi_dev_info *acpi_dev;

@@ -935,14 +935,14 @@ static struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u16 bdf)
		return NULL;

	list_for_each_entry(acpi_dev, &amdgpu_acpi_dev_list, list)
		if (acpi_dev->bdf == bdf)
		if (acpi_dev->sbdf == sbdf)
			return acpi_dev;

	return NULL;
}

static int amdgpu_acpi_dev_init(struct amdgpu_acpi_dev_info **dev_info,
				struct amdgpu_acpi_xcc_info *xcc_info, u16 bdf)
				struct amdgpu_acpi_xcc_info *xcc_info, u32 sbdf)
{
	struct amdgpu_acpi_dev_info *tmp;
	union acpi_object *obj;
@@ -955,7 +955,7 @@ static int amdgpu_acpi_dev_init(struct amdgpu_acpi_dev_info **dev_info,

	INIT_LIST_HEAD(&tmp->xcc_list);
	INIT_LIST_HEAD(&tmp->list);
	tmp->bdf = bdf;
	tmp->sbdf = sbdf;

	obj = acpi_evaluate_dsm_typed(xcc_info->handle, &amd_xcc_dsm_guid, 0,
				      AMD_XCC_DSM_GET_SUPP_MODE, NULL,
@@ -1007,7 +1007,7 @@ static int amdgpu_acpi_dev_init(struct amdgpu_acpi_dev_info **dev_info,

	DRM_DEBUG_DRIVER(
		"New dev(%x): Supported xcp mode: %x curr xcp_mode : %x mem mode : %x, tmr base: %llx tmr size: %llx  ",
		tmp->bdf, tmp->supp_xcp_mode, tmp->xcp_mode, tmp->mem_mode,
		tmp->sbdf, tmp->supp_xcp_mode, tmp->xcp_mode, tmp->mem_mode,
		tmp->tmr_base, tmp->tmr_size);
	list_add_tail(&tmp->list, &amdgpu_acpi_dev_list);
	*dev_info = tmp;
@@ -1023,7 +1023,7 @@ static int amdgpu_acpi_dev_init(struct amdgpu_acpi_dev_info **dev_info,
}

static int amdgpu_acpi_get_xcc_info(struct amdgpu_acpi_xcc_info *xcc_info,
				    u16 *bdf)
				    u32 *sbdf)
{
	union acpi_object *obj;
	acpi_status status;
@@ -1054,8 +1054,10 @@ static int amdgpu_acpi_get_xcc_info(struct amdgpu_acpi_xcc_info *xcc_info,
	xcc_info->phy_id = (obj->integer.value >> 32) & 0xFF;
	/* xcp node of this xcc [47:40] */
	xcc_info->xcp_node = (obj->integer.value >> 40) & 0xFF;
	/* PF domain of this xcc [31:16] */
	*sbdf = (obj->integer.value) & 0xFFFF0000;
	/* PF bus/dev/fn of this xcc [63:48] */
	*bdf = (obj->integer.value >> 48) & 0xFFFF;
	*sbdf |= (obj->integer.value >> 48) & 0xFFFF;
	ACPI_FREE(obj);
	obj = NULL;

@@ -1079,7 +1081,7 @@ static int amdgpu_acpi_enumerate_xcc(void)
	struct acpi_device *acpi_dev;
	char hid[ACPI_ID_LEN];
	int ret, id;
	u16 bdf;
	u32 sbdf;

	INIT_LIST_HEAD(&amdgpu_acpi_dev_list);
	xa_init(&numa_info_xa);
@@ -1107,16 +1109,16 @@ static int amdgpu_acpi_enumerate_xcc(void)
		xcc_info->handle = acpi_device_handle(acpi_dev);
		acpi_dev_put(acpi_dev);

		ret = amdgpu_acpi_get_xcc_info(xcc_info, &bdf);
		ret = amdgpu_acpi_get_xcc_info(xcc_info, &sbdf);
		if (ret) {
			kfree(xcc_info);
			continue;
		}

		dev_info = amdgpu_acpi_get_dev(bdf);
		dev_info = amdgpu_acpi_get_dev(sbdf);

		if (!dev_info)
			ret = amdgpu_acpi_dev_init(&dev_info, xcc_info, bdf);
			ret = amdgpu_acpi_dev_init(&dev_info, xcc_info, sbdf);

		if (ret == -ENOMEM)
			return ret;
@@ -1136,13 +1138,14 @@ int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
			     u64 *tmr_size)
{
	struct amdgpu_acpi_dev_info *dev_info;
	u16 bdf;
	u32 sbdf;

	if (!tmr_offset || !tmr_size)
		return -EINVAL;

	bdf = pci_dev_id(adev->pdev);
	dev_info = amdgpu_acpi_get_dev(bdf);
	sbdf = (pci_domain_nr(adev->pdev->bus) << 16);
	sbdf |= pci_dev_id(adev->pdev);
	dev_info = amdgpu_acpi_get_dev(sbdf);
	if (!dev_info)
		return -ENOENT;

@@ -1157,13 +1160,14 @@ int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
{
	struct amdgpu_acpi_dev_info *dev_info;
	struct amdgpu_acpi_xcc_info *xcc_info;
	u16 bdf;
	u32 sbdf;

	if (!numa_info)
		return -EINVAL;

	bdf = pci_dev_id(adev->pdev);
	dev_info = amdgpu_acpi_get_dev(bdf);
	sbdf = (pci_domain_nr(adev->pdev->bus) << 16);
	sbdf |= pci_dev_id(adev->pdev);
	dev_info = amdgpu_acpi_get_dev(sbdf);
	if (!dev_info)
		return -ENOENT;

+6 −0
Original line number Diff line number Diff line
@@ -748,6 +748,9 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
	ssize_t result = 0;
	int r;

	if (!adev->smc_rreg)
		return -EPERM;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

@@ -804,6 +807,9 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *
	ssize_t result = 0;
	int r;

	if (!adev->smc_wreg)
		return -EPERM;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

+10 −15
Original line number Diff line number Diff line
@@ -1456,14 +1456,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
}

/*
 * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
 * speed switching. Until we have confirmation from Intel that a specific host
 * supports it, it's safer that we keep it disabled for all.
 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
 * don't support dynamic speed switching. Until we have confirmation from Intel
 * that a specific host supports it, it's safer that we keep it disabled for all.
 *
 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
 */
bool amdgpu_device_pcie_dynamic_switching_supported(void)
static bool amdgpu_device_pcie_dynamic_switching_supported(void)
{
#if IS_ENABLED(CONFIG_X86)
	struct cpuinfo_x86 *c = &cpu_data(0);
@@ -1496,20 +1496,13 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
	default:
		return false;
	}
	if (adev->flags & AMD_IS_APU)
		return false;
	if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
		return false;
	return pcie_aspm_enabled(adev->pdev);
}

bool amdgpu_device_aspm_support_quirk(void)
{
#if IS_ENABLED(CONFIG_X86)
	struct cpuinfo_x86 *c = &cpu_data(0);

	return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
#else
	return true;
#endif
}

/* if we get transitioned to only one device, take VGA back */
/**
 * amdgpu_device_vga_set_decode - enable/disable vga decode
@@ -2315,6 +2308,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
		adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
	if (!amdgpu_device_pcie_dynamic_switching_supported())
		adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;

	total = true;
	for (i = 0; i < adev->num_ip_blocks; i++) {
Loading