Commit 633f16d7 authored by Shahar Shitrit's avatar Shahar Shitrit Committed by Jakub Kicinski
Browse files

net/mlx5: Modify LSB bitmask in temperature event to include only the first bit 



In the sensor_count field of the MTEWE register, bits 1-62 are
supported only for unmanaged switches, not for NICs, and bit 63
is reserved for internal use.

To prevent confusing output that may include set bits that are
not relevant to NIC sensors, we update the bitmask to retain only
the first bit, which corresponds to the sensor ASIC.

Signed-off-by: default avatarShahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Reviewed-by: default avatarMateusz Polchlopek <mateusz.polchlopek@intel.com>
Link: https://patch.msgid.link/20250213094641.226501-4-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent b9b72ce0

drivers/net/ethernet/mellanox/mlx5/core/events.c

+4 −0
Original line number Diff line number Diff line
@@ -163,6 +163,10 @@ static int temp_warn(struct notifier_block *nb, unsigned long type, void *data) 
	u64 value_msb;



	value_lsb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb);

	/* bit 1-63 are not supported for NICs,

	 * hence read only bit 0 (asic) from lsb.

	 */

	value_lsb &= 0x1;

	value_msb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb);



	if (net_ratelimit())