Commit 63407d30 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-fixes-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy fixes from Vinod Koul:

 - static checker (array size, bounds) fix for marvel driver

 - Rockchip rk3588 pcie fixes for bifurcation and mux

 - Qualcomm qmp-compbo fix for VCO, register base and regulator name for
   m31 driver

 - charger det crash fix for ti driver

* tag 'phy-fixes-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: ti: tusb1210: Resolve charger-det crash if charger psy is unregistered
  phy: qcom: qmp-combo: fix VCO div offset on v5_5nm and v6
  phy: phy-rockchip-samsung-hdptx: Select CONFIG_RATIONAL
  phy: qcom: m31: match requested regulator name with dt schema
  phy: qcom: qmp-combo: Fix register base for QSERDES_DP_PHY_MODE
  phy: qcom: qmp-combo: Fix VCO div offset on v3
  phy: rockchip: naneng-combphy: Fix mux on rk3588
  phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bits
  phy: rockchip-snps-pcie3: fix bifurcation on rk3588
  phy: freescale: imx8m-pcie: fix pcie link-up instability
  phy: marvell: a3700-comphy: Fix hardcoded array size
  phy: marvell: a3700-comphy: Fix out of bounds read
parents 5eb4573e bf6e4ee5

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

+4 −2
Original line number Diff line number Diff line
@@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
		/* Source clock from SoC internal PLL */

		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);

		if (imx8_phy->drvdata->variant != IMX8MM) {

			writel(AUX_PLL_REFCLK_SEL_SYS_PLL,

			       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);

		}

		val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;

		writel(val | ANA_AUX_RX_TERM_GND_EN,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

+5 −4
Original line number Diff line number Diff line
@@ -603,7 +603,7 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 
	u16 val;



	fix_idx = 0;

	for (addr = 0; addr < 512; addr++) {

	for (addr = 0; addr < ARRAY_SIZE(gbe_phy_init); addr++) {

		/*

		 * All PHY register values are defined in full for 3.125Gbps

		 * SERDES speed. The values required for 1.25 Gbps are almost
@@ -611,10 +611,11 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 
		 * comparison to 3.125 Gbps values. These register values are

		 * stored in "gbe_phy_init_fix" array.

		 */

		if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {

		if (!is_1gbps &&

		    fix_idx < ARRAY_SIZE(gbe_phy_init_fix) &&

		    gbe_phy_init_fix[fix_idx].addr == addr) {

			/* Use new value */

			val = gbe_phy_init_fix[fix_idx].value;

			if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))

			fix_idx++;

		} else {

			val = gbe_phy_init[addr];

drivers/phy/qualcomm/phy-qcom-m31.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ static int m31usb_phy_probe(struct platform_device *pdev) 
		return dev_err_probe(dev, PTR_ERR(qphy->phy),

				     "failed to create phy\n");



	qphy->vreg = devm_regulator_get(dev, "vdda-phy");

	qphy->vreg = devm_regulator_get(dev, "vdd");

	if (IS_ERR(qphy->vreg))

		return dev_err_probe(dev, PTR_ERR(qphy->vreg),

				     "failed to get vreg\n");

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+9 −3
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ enum qphy_reg_layout { 
	QPHY_COM_BIAS_EN_CLKBUFLR_EN,



	QPHY_DP_PHY_STATUS,

	QPHY_DP_PHY_VCO_DIV,



	QPHY_TX_TX_POL_INV,

	QPHY_TX_TX_DRV_LVL,
@@ -102,6 +103,7 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V3_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V3_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V3_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V3_TX_TX_DRV_LVL,
@@ -126,6 +128,7 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V4_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V4_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V4_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V4_TX_TX_DRV_LVL,
@@ -150,6 +153,7 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V5_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V5_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V5_5NM_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V5_5NM_TX_TX_DRV_LVL,
@@ -174,6 +178,7 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V6_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V6_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V6_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V6_TX_TX_DRV_LVL,
@@ -2150,9 +2155,9 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 
	writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);



	if (reverse)

		writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE);

		writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);

	else

		writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE);

		writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);



	return reverse;

}
@@ -2162,6 +2167,7 @@ static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 
	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	u32 phy_vco_div;

	unsigned long pixel_freq;

	const struct qmp_phy_cfg *cfg = qmp->cfg;



	switch (dp_opts->link_rate) {

	case 1620:
@@ -2184,7 +2190,7 @@ static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 
		/* Other link rates aren't supported */

		return -EINVAL;

	}

	writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);

	writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);



	clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);

	clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);

drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v5.h

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#define QCOM_PHY_QMP_DP_PHY_V5_H_



/* Only for QMP V5 PHY - DP PHY registers */

#define QSERDES_V5_DP_PHY_VCO_DIV			0x070

#define QSERDES_V5_DP_PHY_AUX_INTERRUPT_STATUS		0x0d8

#define QSERDES_V5_DP_PHY_STATUS			0x0dc