Commit 637902f7 authored by Michal Simek's avatar Michal Simek
Browse files

arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM 



With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for EMMC
on production SOMs and SD on kv260-revB.

Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf5a4e412e1674500a71a0b1eed7fa8393f37ae9.1683034376.git.michal.simek@amd.com
parent 4a7f7ead

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * Clock specification for Xilinx ZynqMP

 *

 * (C) Copyright 2017 - 2021, Xilinx, Inc.

 * (C) Copyright 2017 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -185,10 +186,12 @@ &sata { 


&sdhci0 {

	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;

	assigned-clocks = <&zynqmp_clk SDIO0_REF>;

};



&sdhci1 {

	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;

	assigned-clocks = <&zynqmp_clk SDIO1_REF>;

};



&spi0 {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+1 −0
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ &sdhci1 { /* on CC with tuned parameters */ 
	no-1-8-v;

	disable-wp;

	xlnx,mio-bank = <1>;

	assigned-clock-rates = <187498123>;

};



&gem3 { /* required by spec */

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ &sdhci1 { /* on CC with tuned parameters */ 
	clk-phase-sd-hs = <126>, <60>;

	clk-phase-uhs-sdr25 = <120>, <60>;

	clk-phase-uhs-ddr50 = <126>, <48>;

	assigned-clock-rates = <187498123>;

};



&gem3 { /* required by spec */

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts

+1 −0
Original line number Diff line number Diff line
@@ -178,6 +178,7 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ 
	disable-wp;

	bus-width = <8>;

	xlnx,mio-bank = <0>;

	assigned-clock-rates = <187498123>;

};



&spi1 { /* MIO6, 9-11 */