Commit 63ab80d9 authored by Rafal Ostrowski's avatar Rafal Ostrowski Committed by Alex Deucher
Browse files

drm/amd/display: DML2.1 Post-Si Cleanup 



[Why]
There are a few cleanup and refactoring tasks that need to be done
with the DML2.1 wrapper and DC interface to remove dependencies on
legacy structures and N-1 prototypes.

[How]
Implemented pipe_ctx->global_sync.
Implemented new functions to use pipe_ctx->hubp_regs and
pipe_ctx->global_sync:
- hubp_setup2
- hubp_setup_interdependent2
- Several other new functions for DCN 4.01 to support newer structures

Removed dml21_update_pipe_ctx_dchub_regs
Removed dml21_extract_legacy_watermark_set
Removed dml21_populate_pipe_ctx_dlg_param
Removed outdated dcn references in DML2.1 wrapper.

Reviewed-by: default avatarAustin Zheng <austin.zheng@amd.com>
Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarRafal Ostrowski <rostrows@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 00d53a0d

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+10 −6
Original line number Diff line number Diff line
@@ -4478,7 +4478,7 @@ static void set_hfvs_info_packet( 
static void adaptive_sync_override_dp_info_packets_sdp_line_num(

		const struct dc_crtc_timing *timing,

		struct enc_sdp_line_num *sdp_line_num,

		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)

		unsigned int vstartup_start)

{

	uint32_t asic_blank_start = 0;

	uint32_t asic_blank_end   = 0;
@@ -4493,8 +4493,8 @@ static void adaptive_sync_override_dp_info_packets_sdp_line_num( 
	asic_blank_end = (asic_blank_start - tg->v_border_bottom -

						tg->v_addressable - tg->v_border_top);



	if (pipe_dlg_param->vstartup_start > asic_blank_end) {

		v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end));

	if (vstartup_start > asic_blank_end) {

		v_update = (tg->v_total - (vstartup_start - asic_blank_end));

		sdp_line_num->adaptive_sync_line_num_valid = true;

		sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);

	} else {
@@ -4507,7 +4507,7 @@ static void set_adaptive_sync_info_packet( 
		struct dc_info_packet *info_packet,

		const struct dc_stream_state *stream,

		struct encoder_info_frame *info_frame,

		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)

		unsigned int vstartup_start)

{

	if (!stream->adaptive_sync_infopacket.valid)

		return;
@@ -4515,7 +4515,7 @@ static void set_adaptive_sync_info_packet( 
	adaptive_sync_override_dp_info_packets_sdp_line_num(

			&stream->timing,

			&info_frame->sdp_line_num,

			pipe_dlg_param);

			vstartup_start);



	*info_packet = stream->adaptive_sync_infopacket;

}
@@ -4548,6 +4548,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 
{

	enum signal_type signal = SIGNAL_TYPE_NONE;

	struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;

	unsigned int vstartup_start = 0;



	/* default all packets to invalid */

	info->avi.valid = false;
@@ -4561,6 +4562,9 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 
	info->adaptive_sync.valid = false;

	signal = pipe_ctx->stream->signal;



	if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

		vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);



	/* HDMi and DP have different info packets*/

	if (dc_is_hdmi_signal(signal)) {

		set_avi_info_frame(&info->avi, pipe_ctx);
@@ -4582,7 +4586,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 
		set_adaptive_sync_info_packet(&info->adaptive_sync,

										pipe_ctx->stream,

										info,

										&pipe_ctx->pipe_dlg_param);

										vstartup_start);

	}



	patch_gamut_packet_checksum(&info->gamut);

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+0 −77
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 
#include "dml21_utils.h"

#include "dml21_translation_helper.h"

#include "bounding_boxes/dcn4_soc_bb.h"

#include "bounding_boxes/dcn3_soc_bb.h"



static void dml21_init_socbb_params(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,
@@ -20,10 +19,6 @@ static void dml21_init_socbb_params(struct dml2_initialize_instance_in_out *dml_ 
	const struct dml2_soc_qos_parameters *qos_params;



	switch (in_dc->ctx->dce_version) {

	case DCN_VERSION_3_2:	// TODO : Temporary for N-1 validation. Remove this after N-1 validation phase is complete.

		soc_bb = &dml2_socbb_dcn31;

		qos_params = &dml_dcn31_soc_qos_params;

		break;

	case DCN_VERSION_4_01:

	default:

		if (config->bb_from_dmub)
@@ -60,9 +55,6 @@ static void dml21_init_ip_params(struct dml2_initialize_instance_in_out *dml_ini 
	const struct dml2_ip_capabilities *ip_caps;



	switch (in_dc->ctx->dce_version) {

	case DCN_VERSION_3_2:	// TODO : Temporary for N-1 validation. Remove this after N-1 validation phase is complete.

		ip_caps = &dml2_dcn31_max_ip_caps;

		break;

	case DCN_VERSION_4_01:

	default:

		ip_caps = &dml2_dcn401_max_ip_caps;
@@ -1091,28 +1083,6 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state 
	context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;

}



void dml21_extract_legacy_watermark_set(const struct dc *in_dc, struct dcn_watermarks *watermark, enum dml2_dchub_watermark_reg_set_index reg_set_idx, struct dml2_context *in_ctx)

{

	struct dml2_core_internal_display_mode_lib *mode_lib = &in_ctx->v21.dml_init.dml2_instance->core_instance.clean_me_up.mode_lib;

	double refclk_freq_in_mhz = (in_ctx->v21.display_config.overrides.hw.dlg_ref_clk_mhz > 0) ? (double)in_ctx->v21.display_config.overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz;



	if (reg_set_idx >= DML2_DCHUB_WATERMARK_SET_NUM) {

		/* invalid register set index */

		return;

	}



	/* convert to legacy format (time in ns) */

	watermark->urgent_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].urgent / refclk_freq_in_mhz) * 1000.0;

	watermark->pte_meta_urgent_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].urgent / refclk_freq_in_mhz) * 1000.0;

	watermark->cstate_pstate.cstate_enter_plus_exit_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].sr_enter / refclk_freq_in_mhz) * 1000.0;

	watermark->cstate_pstate.cstate_exit_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].sr_exit / refclk_freq_in_mhz) * 1000.0;

	watermark->cstate_pstate.pstate_change_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].uclk_pstate / refclk_freq_in_mhz) * 1000.0;

	watermark->urgent_latency_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].urgent / refclk_freq_in_mhz) * 1000.0;

	watermark->cstate_pstate.fclk_pstate_change_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].fclk_pstate / refclk_freq_in_mhz) * 1000.0;

	watermark->frac_urg_bw_flip = in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].frac_urg_bw_flip;

	watermark->frac_urg_bw_nom = in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].frac_urg_bw_nom;

}



static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)

{

	struct dml2_dchub_watermark_regs *wm_regs = NULL;
@@ -1156,53 +1126,6 @@ void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_se 
	}

}





void dml21_populate_pipe_ctx_dlg_params(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming)

{

	unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end;

	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

	union dml2_global_sync_programming *global_sync = &stream_programming->global_sync;



	hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right + pipe_ctx->hblank_borrow;

	vactive = timing->v_addressable + timing->v_border_bottom + timing->v_border_top;

	hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;

	vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;



	hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right - pipe_ctx->hblank_borrow;

	vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;



	if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

		/* phantom has its own global sync */

		global_sync = &stream_programming->phantom_stream.global_sync;

	}



	pipe_ctx->pipe_dlg_param.vstartup_start = global_sync->dcn4x.vstartup_lines;

	pipe_ctx->pipe_dlg_param.vupdate_offset = global_sync->dcn4x.vupdate_offset_pixels;

	pipe_ctx->pipe_dlg_param.vupdate_width = global_sync->dcn4x.vupdate_vupdate_width_pixels;

	pipe_ctx->pipe_dlg_param.vready_offset = global_sync->dcn4x.vready_offset_pixels;

	pipe_ctx->pipe_dlg_param.pstate_keepout = global_sync->dcn4x.pstate_keepout_start_lines;



	pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;



	pipe_ctx->pipe_dlg_param.hactive = hactive;

	pipe_ctx->pipe_dlg_param.vactive = vactive;

	pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;

	pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;

	pipe_ctx->pipe_dlg_param.hblank_end = hblank_end;

	pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;

	pipe_ctx->pipe_dlg_param.hblank_start = hblank_start;

	pipe_ctx->pipe_dlg_param.vblank_start = vblank_start;

	pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;

	pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;

	pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;

	pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max;

	pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min;

	pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height;

	pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width;

	pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height;

	pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width;

}



void dml21_map_hw_resources(struct dml2_context *dml_ctx)

{

	unsigned int i = 0;

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

+0 −2
Original line number Diff line number Diff line
@@ -21,8 +21,6 @@ void dml21_initialize_soc_bb_params(struct dml2_initialize_instance_in_out *dml_ 
void dml21_initialize_ip_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);

void dml21_populate_pipe_ctx_dlg_params(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming);

void dml21_extract_legacy_watermark_set(const struct dc *in_dc, struct dcn_watermarks *watermark, enum dml2_dchub_watermark_reg_set_index reg_set_idx, struct dml2_context *in_ctx);

void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);

void dml21_map_hw_resources(struct dml2_context *dml_ctx);

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c

+15 −114
Original line number Diff line number Diff line
@@ -142,108 +142,21 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc, 
	return num_pipes;

}





void dml21_update_pipe_ctx_dchub_regs(struct dml2_display_rq_regs *rq_regs,

	struct dml2_display_dlg_regs *disp_dlg_regs,

	struct dml2_display_ttu_regs *disp_ttu_regs,

	struct pipe_ctx *out)

void dml21_pipe_populate_global_sync(struct dml2_context *dml_ctx,

	struct dc_state *context,

	struct pipe_ctx *pipe_ctx,

	struct dml2_per_stream_programming *stream_programming)

{

	memset(&out->rq_regs, 0, sizeof(out->rq_regs));

	out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size;

	out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size;

	//out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size;

	//out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size;

	out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size;

	out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size;

	out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height;

	out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear;



	out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size;

	out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size;

	//out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size;

	//out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size;

	out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size;

	out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size;

	out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height;

	out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear;



	out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode;

	out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode;

	//out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode;

	out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode;

	out->rq_regs.plane1_base_address = rq_regs->plane1_base_address;

	out->unbounded_req = rq_regs->unbounded_request_enabled;



	memset(&out->dlg_regs, 0, sizeof(out->dlg_regs));

	out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end;

	out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end;

	out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;

	out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal;

	out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler;

	out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler;

	out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch;

	out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank;

	out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank;

	out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip;

	out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip;

	out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq;

	out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch;

	out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c;

	out->dlg_regs.refcyc_per_tdlut_group = disp_dlg_regs->refcyc_per_tdlut_group;

	out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l;

	out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c;

	//out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;

	//out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c;

	out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l;

	out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c;

	//out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l;

	//out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c;

	out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l;

	out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c;

	out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l;

	out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c;

	//out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l;

	//out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c;

	//out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l;

	//out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c;

	out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l;

	out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c;

	out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l;

	out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c;

	out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank;

	out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip;

	out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank;

	out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip;

	out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0;

	out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0;

	//out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1;

	//out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1;

	out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;

	out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit;

	out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata;

	out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta;



	memset(&out->ttu_regs, 0, sizeof(out->ttu_regs));

	out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm;

	out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;

	out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank;

	out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip;

	out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l;

	out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c;

	out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0;

	//out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1;

	out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l;

	out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c;

	out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0;

	//out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1;

	out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l;

	out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c;

	out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0;

	//out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1;

	out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l;

	out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c;

	out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0;

	//out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1;

	union dml2_global_sync_programming *global_sync = &stream_programming->global_sync;



	if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

		/* phantom has its own global sync */

		global_sync = &stream_programming->phantom_stream.global_sync;

	}



	memcpy(&pipe_ctx->global_sync,

		global_sync,

		sizeof(union dml2_global_sync_programming));

}



void dml21_populate_mall_allocation_size(struct dc_state *context,
@@ -301,28 +214,16 @@ void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *contex 
{

	unsigned int pipe_reg_index = 0;



	dml21_populate_pipe_ctx_dlg_params(dml_ctx, context, pipe_ctx, stream_prog);

	dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);

	find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index);



	if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

		memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

		pipe_ctx->unbounded_req = false;



		/* legacy only, should be removed later */

		dml21_update_pipe_ctx_dchub_regs(&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->rq_regs,

				&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->dlg_regs,

				&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->ttu_regs, pipe_ctx);



		pipe_ctx->det_buffer_size_kb = 0;

	} else {

		memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

		pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled;



		/* legacy only, should be removed later */

		dml21_update_pipe_ctx_dchub_regs(&pln_prog->pipe_regs[pipe_reg_index]->rq_regs,

				&pln_prog->pipe_regs[pipe_reg_index]->dlg_regs,

				&pln_prog->pipe_regs[pipe_reg_index]->ttu_regs, pipe_ctx);



		pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64;

	}

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.h

+4 −4
Original line number Diff line number Diff line
@@ -18,10 +18,10 @@ struct dml2_display_ttu_regs; 
int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id);

int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id);

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);

void dml21_update_pipe_ctx_dchub_regs(struct dml2_display_rq_regs *rq_regs,

	struct dml2_display_dlg_regs *disp_dlg_regs,

	struct dml2_display_ttu_regs *disp_ttu_regs,

	struct pipe_ctx *out);

void dml21_pipe_populate_global_sync(struct dml2_context *dml_ctx,

		struct dc_state *context,

		struct pipe_ctx *pipe_ctx,

		struct dml2_per_stream_programming *stream_programming);

void dml21_populate_mall_allocation_size(struct dc_state *context,

		struct dml2_context *in_ctx,

		struct dml2_per_plane_programming *pln_prog,