Commit 63b8c9fd authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/vcn2.5: implement ring reset 



Use the new helpers to handle engine resets for VCN.

Reviewed-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Tested-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64ac0097

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+25 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 
				   struct dpg_pause_state *new_state);

static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);

static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);

static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst);



static int amdgpu_ih_clientid_vcns[] = {

	SOC15_IH_CLIENTID_VCN,
@@ -404,8 +405,14 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) 


		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)

			adev->vcn.inst[j].pause_dpg_mode = vcn_v2_5_pause_dpg_mode;

		adev->vcn.inst[j].reset = vcn_v2_5_reset;

	}



	adev->vcn.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);

	if (!amdgpu_sriov_vf(adev))

		adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;



	if (amdgpu_sriov_vf(adev)) {

		r = amdgpu_virt_alloc_mm_table(adev);

		if (r)
@@ -425,6 +432,10 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->vcn.ip_dump = ptr;

	}



	r = amdgpu_vcn_sysfs_reset_mask_init(adev);

	if (r)

		return r;



	return 0;

}
@@ -455,6 +466,8 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) 
	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_free_mm_table(adev);



	amdgpu_vcn_sysfs_reset_mask_fini(adev);



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		r = amdgpu_vcn_suspend(adev, i);

		if (r)
@@ -1816,6 +1829,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 
	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,

	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

	.reset = amdgpu_vcn_ring_reset,

};



/**
@@ -1914,6 +1928,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 
	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,

	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

	.reset = amdgpu_vcn_ring_reset,

};



static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
@@ -1942,6 +1957,16 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 
	}

}



static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst)

{

	int r;



	r = vcn_v2_5_stop(vinst);

	if (r)

		return r;

	return vcn_v2_5_start(vinst);

}



static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;