Commit 63d5f8db authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
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drm/amdgpu: Enable devcoredump for JPEG2_0_0 



Add register list and enable devcoredump for JPEG2_0_0

V2: (Lijo)
- remove version specific callbacks and use simplified helper functions

V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d949e91b

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

+22 −0
Original line number Diff line number Diff line
@@ -33,6 +33,22 @@ 
#include "vcn/vcn_2_0_0_sh_mask.h"

#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"



static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = {

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),

	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),

};



static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);

static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);

static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
@@ -98,6 +114,10 @@ static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) 
	adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;

	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);



	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0));

	if (r)

		return r;



	return 0;

}
@@ -752,6 +772,8 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 
	.wait_for_idle = jpeg_v2_0_wait_for_idle,

	.set_clockgating_state = jpeg_v2_0_set_clockgating_state,

	.set_powergating_state = jpeg_v2_0_set_powergating_state,

	.dump_ip_state = amdgpu_jpeg_dump_ip_state,

	.print_ip_state = amdgpu_jpeg_print_ip_state,

};



static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {